Semiconductor memory device

ABSTRACT

A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [ 2 ], and a storage block is selected with external address bit AA [ 23 ]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and, inparticular, relates to a nonvolatile semiconductor memory device thatcan store multi-level data having three or more levels in a nonvolatilemanner. More specifically, the present invention relates to aconfiguration for implementing a multi-level nonvolatile semiconductormemory device that stores multi-level data by utilizing an internalconfiguration of a nonvolatile semiconductor memory device for storingbinary data.

2. Description of the Background Art

In a nonvolatile semiconductor memory device for storing data in anonvolatile manner, a memory cell is formed of a single transistor. Sucha memory cell transistor has a floating gate that is formed between acontrol gate and a substrate region. This floating gate is electricallyisolated from its surrounding and the threshold voltage of the memorycell transistor is determined depending on the amount of charges(electrons) accumulated in the floating gate. In a memory cell (SingleLevel Cell: SLC) for storing binary data of “1” and “0,” the states of ahigh threshold voltage and a low threshold voltage are correlated witheach data value of the binary data. Generally, the state of a lowthreshold voltage is referred to as an erased state and is correlatedwith data “1”, while the state of a high threshold voltage is referredto as a programmed state (written state) and is correlated with thestate where data “0” is stored.

A nonvolatile memory cell is formed of one transistor and therefore, hasan advantages that the area occupied by the cell is small and data canbe stored in a nonvolatile manner.

In order to store a large amount of data such as audio data and videodata, it is required to increase the storage capacity. In order tosatisfy such requirement, the specification of a multi-level memory cell(MLC: Multi-Level Cell) for storing data of two or more bits in onememory cell has been implemented. Multi-level data (data formed of twoor more bits) instead of binary data is stored in a memory cell andtherefore, the storage capacity can be increased while suppressing anincrease in the area of the memory device. Such a nonvolatilesemiconductor memory device for storing multi-level data is disclosedin, for example, Prior Art Document I (Japanese Patent Laying-Open No.2001-6375), Prior Art Document 2 (Japanese Patent Laying-Open No.11-25682) and others.

Document 1 discloses a configuration for storing multi-level data bycompressing data supplied via the same data terminal at differenttimings, to produce compressed data for writing into a memory cell.

In the configuration disclosed in Document 2, predetermined operationalprocessing is applied to 2 bit data at the time when storage data isproduced, so that the data is converted to 4-level data that correspondto threshold voltage levels. Data writing is performed by extractingcharges (electrons) from the floating gate in accordance with bit “1”that is included in this 4-level data. The storage data of a latchcircuit that is arranged corresponding to a corresponding senseamplifier is set at bit “0” when writing is completed. Writing iscompeted when the entire data of the latch circuits are set to thewriting completed state. Read out of data is performed by changing thevoltage of a word line in multiple stages in data reading out.

Furthermore, Prior Art Document 3 (Japanese Patent Laying-Open No.10-92186) discloses a configuration in which each of the thresholdvoltages is correlated with gray code data sequentially starting fromthe lowest threshold voltage when multi-level data is stored. Datadetection in binary searching method in data read out is made easy bycorrelating the gray-coded data to the threshold voltages. A latchcircuit is provided corresponding to each of the bit lines, so thatlatch data in the latch circuit is verified in accordance with thelatched data of the latch circuit and the read-out data for verificationin data writing and then the latched data is set at the write-incompleted state when the latched data and the read-out data coincidewith each other so as to carry out the programming only on memory cellswhere programming is required.

Prior Art Document 4 (Japanese Patent Laying-Open No. 10-55688)discloses a NAND type flash memory provided with a page buffer in orderto carry out data writing in page units. In this Document 4, data readout is performed by one value at a time by varying the word line voltagesequentially and after this read-out, an addition circuit is used toconvert the multi-level data into multi-bit data for storage in thepage-buffer.

Prior Art Document 5 (Japanese Patent Laying-Open No. 7-37393) disclosesa serial sense circuit that reads out data serially from one memory cellby using a sense amplifier in read-out of multi-level data. Inthis-serial sense circuit, a reference voltage and a memory cellread-out potential are compared, and the next comparison referencevoltage is selected in accordance with the result of the comparison andis again compared with the memory cell read-out voltage. Thus, storagedata, or 2-bit data in the case of 4-level data, in a single memory-cellare sequentially read-out.

Prior Art Document 6 (Japanese Patent Laying-Open No. 6-309890)discloses a nonvolatile semiconductor memory device that switches thestorage between 4-level data and 2-level (binary) data in accordancewith a control signal. In the configuration shown in the Document 6, asense circuit is provided exclusively to each mode for 2-level data and4-level data and the write voltage levels for bit lines are switchedbetween 2-value mode and 4-value mode in accordance with the controlsignal instructing 4 levels or 2 levels in the program circuit. Document6 shows a configuration for accessing one memory cell.

It is desirable to implement an SLC configuration and an MLCconfiguration in the same chip from the view points of productmanagement and design efficiency. However, in Documents 1 and 2, onlythe configuration of a multi-level memory is taken into account whilethe structure for coexisting an SLC configuration and an MLCconfiguration is not taken into consideration.

In addition, data conversion is performed such that bits in the samepositions of different data are written in one memory cell in Documents1, 2 and 6. In such a case, one memory cell stores data bits ofdifferent addresses to make the allocations of addresses complicated andtherefore, it becomes difficult to coexist an SLC configuration and anMLC configuration that are different in number of address bits In theconfiguration shown in Document 3, the data stored in a memory cell isconverted into a gray code in accordance with threshold voltages.However, the configuration shown in this Document 3, relates to acircuit for carrying out data writing in page (word line) units bystoring write data in latch circuit provided corresponding to each bitline, and the configuration for data writing in byte units is not takeninto consideration. In addition, allocation of addresses for switchingbetween an SLC configuration and an MLC configuration or coexistence ofSLC configuration and MLC configuration is not taken into consideration.

In Document 4, a page buffer is utilized for converting two-bit data tofour values to perform data writing one level (value ) at a time, whileone value is read out at a time by sequentially varying the word linevoltage upon data read out so that two-bit data is generated based onthe result of this read-out. In data read out the word line voltage ischanged and a problem arises that a long period of time is required fordata read-out. In addition, allocation of addresses is not taken intoconsideration in this Document 4, too.

In Document 5, a sense amplifier is used and the comparison basispotential serving as the comparison reference for the memory cellpotential is changed to read out data in the same memory cell in aserial manner. However, the configuration for stably generating thebasis voltage for the comparison is not taken into consideration. Inaddition, allocation of addresses for allowing the coexistence of an SLCconfiguration and an MLC configuration is not taken into consideration.

Document 6 shows a configuration for switching an SLC configuration andan MLC configuration by means of a control signal. However, input/outputof data is performed in units of one bit or two bits in theconfiguration disclosed in this Document 6 and a configuration forwriting in and for reading out data words in byte units is not takeninto consideration. In addition, a sense amplifier for reading out4-level data and a sense amplifier for reading out 2-level data areseparately provided in the configuration shown in this Document 6 andtherefore, the circuit configuration is redundant and a problem ofincreased circuit layout area arises. Moreover, efficient allocation ofaddresses for allowing the coexistence of SLC configuration and an MLCconfiguration is not taken into consideration.

Further, Documents 1 to 3 and 6 show a NAND type flash memory in whichdata writing is performed in page units and do not show a configurationof an NOR-type flash memory wherein data writing is performed byutilizing channel hot electrons. In addition, a configuration forimplementing both the page mode operation and the random accessoperation in such a memory device is not taken into consideration.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a nonvolatilesemiconductor memory device of an MLC configuration, compatible with anSLC configuration, for allowing writing and reading of multi-level dataat high speed.

Another object of the present invention is to provide a nonvolatilesemiconductor memory device of an MLC configuration allowing stable dataread out in a page mode according to a serial sense scheme.

According to a first aspect of the present invention, a semiconductormemory device includes an address conversion circuit that uses a firstbit of an address signal as a block selecting address bit in a firstoperation mode, uses the first bit of the address signal as an addressbit indicating the order in which multi-bit data are supplied in asecond operation mode, and uses the second bit of the address signal asa block selecting address bit in the second operation mode.

According to a second aspect of the present invention, a semiconductormemory device includes: a plurality of memory cells aligned in rows andcolumns; a plurality of reference cells; and a current/voltageconversion circuit which averages currents flowing through thesereference cells and converts the averaged current into a voltage forgenerating a reference voltage.

According to a third aspect of the present invention, a semiconductormemory device includes: a plurality of memory cells arranged in rows andcolumns; a plurality of word lines arranged corresponding to therespective memory cell rows and having the memory cells in thecorresponding rows connected; a circuit for dividing a first voltage ata predetermined voltage level that is transmitted onto a selected wordline; a reference cell that is selectively made conductive in accordancewith the divided voltage; a reference voltage generation circuit forgenerating a reference voltage in accordance with a current that flowsthrough the reference cell; and a sense amplifier circuit for generatinga comparison reference current in accordance with the reference voltageand comparing this comparison reference current with the current thatflows through the selected memory cell to sense the memory cell data.

According to a fourth aspect of the present invention, a semiconductormemory device includes: a plurality of memory cells divided into aplurality of blocks; a memory cell selection circuit for selecting amemory cell; a plurality of sense amplifier circuits arrangedcorresponding to each of the blocks for sensing data of the memory cellselected by the memory cell selection circuit; a first latch circuit forlatching sensed data from the plurality of sense amplifier circuits inaccordance with a first operation timing signal; and a second latchcircuit for latching and storing the sensed data from the plurality ofsense amplifier circuits in accordance with a second operation timingsignal.

The semiconductor memory device according to the fourth aspect of thepresent invention further includes a sense control circuit foractivating the sense amplifier circuits in accordance with first andsecond operation timing with respect to a common address.

According to a fifth aspect of the present invention, a semiconductormemory device includes: a sense amplifier circuit for comparing a cellcurrent driven by a selected memory cell with a reference current tosense data of the selected memory cell in accordance with a result ofcomparison; a sense control circuit for activating the sense amplifiercircuit a number of times for a common address; and a circuit forsetting a second time reference current amount in accordance with firsttime sense data of the sense amplifier circuit.

The first bit and the second bit of an address signal are switched inthe second operation mode and thereby an increase in the address signalbit in the case when the SLC configuration is utilized for the MLCconfiguration can be easily accommodated without changing the internalconfiguration. In addition, a block address bit is utilized so that datain successive addresses can be stored in each block even in the MLCconfiguration.

Currents that flow through a plurality of reference cells are averagedand a reference voltage is generated in accordance with the averagedcurrents. Thus, a reference voltage at a desired voltage level can bestably generated without being affected by variation of thecharacteristics of the reference cells.

A divided voltage is transmitted so that an averaged current at adesired level can be generated to produce a reference voltage withoutchanging the sizes and the threshold voltages of the reference cells.

A sense amplifier circuit is arranged corresponding to each memory blockand the data from the sense amplifier circuit is transferred to thefirst and second latch circuits for the same address. Thus, read out ofdata can be performed in the serial sense scheme even in storage ofmulti-bit data, and in addition, data read out in a page mode can beeasily implemented.

When memory cell data is detected in the serial sense scheme, secondtime reference current is set in accordance with first time sensed dataand thereby, data can be precisely sensed by the sense amplifier circuitfor each word bit without changing the word line voltage.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically showing the allocation of address bitsof a word in an SLC configuration;

FIG. 2 is a diagram schematically showing the allocation of address bitsof a word in an MLC configuration;

FIG. 3 is a diagram schematically showing the correspondencerelationship between words of separation and exchange in an externalprocessing device and words of storage data;

FIG. 4 is a diagram schematically showing the entire configuration of anonvolatile semiconductor memory device according to the presentinvention;

FIG. 5 is a diagram illustrating the correspondence relationship betweenthe external data and the internal data of the MLC configuration as wellas the writing operation according to the present invention;

FIG. 6 is a diagram schematically showing the correspondencerelationship between the storage data and external words of thesemiconductor memory device according to the present invention;

FIG. 7 is a diagram showing an example of a changing sequence ofexternal addresses and internal addresses in data setup in a pagebuffer;

FIG. 8 is a diagram schematically showing the configuration of a pagebuffer shown in FIG. 4;

FIG. 9 is a diagram schematically showing the configuration of the pagebuffer array shown in FIG. 8;

FIG. 10 is a diagram showing an example of the configuration of a pagebuffer control signal generation part in the page buffer control circuitshown in FIG. 4;

FIG. 11 is a diagram showing the correspondence relationship between thelogic levels of the page buffer array control signals shown in FIG. 9and the operation modes;

FIG. 12 is a diagram schematically showing the configuration of the wordline selection circuit shown in FIG. 8;

FIG. 13 is a diagram showing an example of the configuration of the partthat generates a word line selection signal shown in FIG. 12;

FIG. 14 is a diagram showing an example of the configuration of a pageword line clear control signal generation part shown in FIG. 12;

FIG. 15 is a diagram schematically showing the configuration of the wordline selection circuit shown in FIG. 8;

FIG. 16 is a diagram schematically showing the configuration of a pagebuffer write-in/read-out circuit shown in FIG. 8;

FIG. 17 is a diagram schematically showing the configuration of a pagebuffer sense/drive circuit shown in FIG. 16;

FIG. 18 is a diagram showing an example of the configuration of the partthat generates a page buffer setup activation signal shown in FIG. 14;

FIG. 19 is a diagram showing an example of the configuration of the partthat generates a bit line drive control signal shown in FIG. 16;

FIG. 20 is a signal waveform diagram representing an operation of thecircuit shown in FIG. 19;

FIG. 21 is a diagram showing an example of the configuration of a dataconversion circuit shown in FIG. 4;

FIG. 22 is a diagram schematically showing the operation of a dataconversion circuit shown in FIG. 21;

FIG. 23 is a diagram showing an example of the configuration of a datadegeneration part that is included in the data conversion circuit shownin FIG. 4;

FIG. 24 is a diagram showing the correspondence relationship between4-level data and the threshold voltages of a memory cell;

FIG. 25 is a diagram schematically showing the configuration of the mainportion of an OSC circuit and a command user interface shown in FIG. 4;

FIG. 26 is a diagram schematically showing the configuration of the partthat generates a voltage at the time of programming;

FIG. 27 is a diagram showing the write-in sequence of a data word in thedata writing into the memory cell array;

FIG. 28 is a timing chart representing an operation of the data readingout from the memory cell array in verification;

FIG. 29 is a diagram showing an example of the configuration of the partthat generates page buffer data included in a verification circuit shownin FIG. 4;

FIG. 30 is a diagram showing one example of the configuration of theportion that generates the clock signal shown in FIG. 25;

FIG. 31 is a diagram showing an example of the configuration of the partthat generates a verification control signal of the verification circuitshown in FIG. 4;

FIG. 32 is a signal waveform diagram representing an operation of thecircuit shown in FIG. 31 in the verification operation;

FIG. 33 is a diagram schematically showing the configuration of averification data read-out part of the nonvolatile semiconductor memorydevice according to the present invention;

FIG. 34 is a diagram schematically showing the configuration of theverification circuit shown in FIG. 4;

FIG. 35 is a diagram schematically illustrating a conversion sequence ofthe threshold voltage and the verification operation in the programmingoperation;

FIG. 36 is a diagram showing an example of the configuration of acomparison circuit shown in FIG. 34;

FIG. 37 is a diagram showing the relationship between the operationmodes of the comparison circuit shown in FIG. 36 and the control signalsin the respective mode;

FIG. 38 is a diagram showing an example of the configuration of adetermination circuit shown in FIG. 34;

FIG. 39 is a diagram showing an example of the configuration of awrite-in data generation circuit shown in FIG. 34;

FIG. 40 is a diagram showing an example of the configuration of averification sense amplifier;

FIG. 41 is a diagram showing the reference voltage required in theverification operation;

FIG. 42 is a signal waveform diagram representing an operation of averification sense amplifier shown in FIG. 40;

FIG. 43 is a diagram schematically showing the configuration of anotherverification sense amplifier;

FIG. 44 is a signal waveform diagram representing a showing the signalwave operation of a verification sense amplifier shown in FIG. 43;

FIG. 45 is a diagram showing an example of the configuration of the partthat generates a sense control signal for the verification senseamplifier shown in FIG. 43;

FIG. 46 is a diagram showing another modification of the verificationsense amplifier;

FIG. 47 is a diagram illustrating the reference voltages utilized in theverification sense amplifier shown in FIG. 46;

FIG. 48 is a signal waveform diagram representing an operation of averification sense amplifier shown in FIG. 46;

FIG. 49 is a diagram schematically representing another operationsequence of the verification sense amplifier shown in FIG. 46;

FIG. 50 is a diagram schematically showing the configuration of theportion that generates a reference voltage according to the presentinvention;

FIG. 51 is a diagram showing an example of the configuration of thereference voltage generation array shown in FIG. 50;

FIG. 52 is a diagram showing an example of the configuration of thereference cell shown in FIG. 51;

FIG. 53 is a diagram schematically showing the configuration of areference current generation part of the reference array block shown inFIG. 51;

FIG. 54 is a diagram showing another configuration of the referencevoltage generation part;

FIG. 55 is a diagram schematically showing still another configurationof the reference voltage generation part;

FIG. 56 is a diagram showing further another configuration of thereference cell;

FIG. 57 is a diagram showing still another configuration of thereference cell;

FIG. 58 is a diagram schematically showing the configuration of the partrelated to an external data reading out in the semiconductor memorydevice according to the present invention;

FIG. 59 is a diagram schematically showing the configurations of a dataread-out circuit and a data transfer output circuit shown in FIG. 58;

FIG. 60 is a signal waveform diagram representing an operation of aread-out circuit and a data output transfer circuit shown in FIG. 59;

FIG. 61 is a diagram showing an example of the configuration of the partthat generates the sense amplifier selection activation signal shown inFIG. 59;

FIG. 62 is a diagram showing an example of the configuration of the dataselection circuit and selected signal generation part shown in FIG. 59;and

FIG. 63 is a diagram showing an example of the configuration of the partthat generates the data transfer control signal shown in FIG. 59.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1 is a diagram schematically showing the configuration of a memoryarray and the configuration of an address of a memory cell of asemiconductor memory device to which the present invention is applied.In FIG. 1, a memory array MA has memory cells of 8M words×16 bits. Here,1 word is formed of 16 bits.

In memory array MA, 128 blocks of 64K words are provided. Accordingly,an address A [22:0] of 23 bits is used for selecting 1 word from these8M words. Memory array MA is typically divided into two memory mats.Address bits A [22:16] are used for selecting a block SMA of 64K words.64K word block SMA includes two 32K word blocks BAL. The 32K word blockBAL is typically used as a sector and utilized as an erasure unit ofdata.

A read out data block RBK of 8 words is selected from 32K word block BALin data reading out. Address bits A [14:3] are utilized for selectingthe 8 words from 32K word block BAL. Address bits A [2:0] are utilizedfor finally selecting a read out data block ODK by selecting 1 word fromread out data block RBK of 8 words and thus data D of 16 bits isultimately outputted..

Data of 16 bits is stored in memory cells of 16 bits in the SLCconfiguration of the memory array shown in FIG. 1. It is now beconsidered to utilize the semiconductor memory device of this SLCconfiguration as a semiconductor memory device of the MLC configuration.In particular, 4-level data or 2-bit data is assumed to be stored in onememory cell in the MLC configuration. In this case, as shown in FIG. 2,data of 32 bits is stored in memory cells of 16 bits. Specifically, anupper word UW and a lower word LW are stored in the memory cells of 16bits. These upper word UW of 16 bits and lower word LW of 16 bits arewords having different addresses in an external logical space, but arestored in memory cells of the same address in the memory space.

If the address allocation as shown in this FIG. 1 is utilized for theMLC configuration for storing multi-level data, the storage capacity ofdata becomes doubled and therefore additional address bit A [23] becomesnecessary. It is now considered utilize this address bit [23] withoutadversely affecting the SLC configuration. In this case, as describedlater, 32K word block BAL is divided into 2 blocks by address bit A [2].For this block selection, external address bit AA [23] is converted intointernal block address bit A [2] so as to be utilized as a blockselection bit. On the other hand, external address bit AA [2] isutilized as an internal address bit AE [23] for selecting upper word UWand lower word LW.

With such address bit allocation, internal address bit AE [23] isutilized in a data read out part for selection of upper word UW andlower word LW. In the programming operation for writing data, 32-bitdata of upper word UW and lower word LW is compressed into data of 16bits and programming is performed. Accordingly, the same memory addressspace is shared between the SLC configuration and the MLC configurationwith respect to the programming of data and therefore address bit AO[23] for designating the upper and lower words is unnecessary inprogramming.

With such address allocation, only the configuration is required forcontrolling the operation of selecting upper word UW and lower word LWby using a new internal address bit AE [23] when 1 word is selected fromthe 8 words shown in FIG. 1. The other address bits are the same betweenthe SLC configuration and the MLC configuration, and an MLCconfiguration for storing 4-level data can be implemented by utilizingthe SLC configuration.

In addition, as shown in FIG. 2, upper word UW and lower word LW are seach written into different 8-bit cells in 16-bit cells and accordingly,data at the same value of address bit AA [23] can be stored in an upperbyte data storage region and a lower byte data storage region within thecommon block. Accordingly, as shown in FIG. 3, with address bit AA [23]being converted into internal address bits AE [2] and AO [2], the upperaddress space and the lower address space in a logical space AS arerespectively made corresponding to separate blocks in the memory addressspace. Specifically, as shown in FIG. 3, successive 2 words in the samesub-logic space in sub-logic spaces AS0 and AS1 respectively designatedby address bit AA [23] being “0” and “1” can be stored respectively inthe upper sub-logic space word storage block region and in the lowersub-logic space word block region in the memory array. Successiveexternal 2 words in the same sub-logic space can be distributedly storedin the upper byte region and lower byte region, respectively, at thesame address of the block region of the memory array.

In memory cells of 1 word, the upper byte region and the lower byteregion are designated by internal address bit AE [23] corresponding toexternal address bit AA [2]. As a result, allocation of addresses of theinternal address bits becomes simplified and in addition, the matchingof addresses between the memory space and the logic space can beestablished in the MLC configuration. In addition, as described indetail later, the upper word and the lower word of successive 2 wordscan be readily identified when memory cell data is read out inaccordance with the serial sense scheme and the data can be read outeasily in the page mode.

FIG. 4 schematically shows an entire configuration of the nonvolatilesemiconductor memory device according to the first embodiment of thepresent invention. In FIG. 4, a nonvolatile semiconductor memory device1 includes: a memory cell array 10 having a plurality of nonvolatilememory cells arranged in rows and columns; a command user interface(CUI) 2 receiving a command and an address externally applied forgenerating various control signals required for an internal operation;an OSC circuit 3 including an oscillator that oscillates at apredetermined period under control of command user interface (CUI) 2 forgenerating an internal clock signal; and a control unit (CPU) 4 forperforming operations required for a variety of internal operations,such as erasure, verifications and programming, in synchronization withoscillation signal (clock signal) from OSC circuit 3. The CPU 4 controlsthe generation of internal signals and internal voltages which arenecessary for erasure, programming, verifications and read-out inaccordance with an operational mode instruction supplied from commanduser interface (CUI) 2.

Non-volatile semiconductor memory device 1 further includes a dataconversion circuit 8 that transform the bit positions of externallyapplied 16-bit data (word data) in units of 2 words for storage in apage buffer 6 and compresses 32-bit data read out from page buffer 6into 16-bit data for application to a write driver 9. This dataconversion circuit 8 carries out data conversion such that the bits ofthe same word in 2-word data supplied successively are aligned andstores the converted data in page buffer 6, and in addition, compresses32-bit data (2 words) stored in the page buffer into 16-bit data. As aresult, upper word UW and lower word LW, as shown in FIG. 2, suppliedsuccessively are stored, respectively in the upper byte position andlower byte position of the 16-bit memory cells.

Write driver 9 writes 16-bit data supplied from the data conversioncircuit 8 in selected memory cells of memory cell array 10.

The nonvolatile semiconductor memory device 1 further includes averification circuit 5 that verifies whether write-data is preciselywritten into the address upon data writing. Although the operation ofverification circuit 5 will be described later in detail, thisverification circuit 5 receives write-in data of two words from pagebuffer 6 and verification-read data of two words from memory cell array10, and detects the coincidence/non-coincidence for all bits of thereceived data and writes data in page buffer 6 with the value of bitsindicating the write (programming) completion based on the determinationresult. Data conversion circuit 8 again carries out data conversion uponprogramming for application to write driver 9. Therefore, write driver 9applies a high voltage to bit lines only for the memory cells thatrequire programming in data writing.

Programming is performed in units of 16-bit memory cells in memory cellarray 10 while utilizing channel hot electrons (CHE). Programmingindicates an operation of increasing a threshold voltage while erasureindicates an operation of decreasing a threshold voltage.

The data writing operation (that includes verification operation) tomemory cell array 10 will first be briefly described, and then theconfigurations of the circuits will be described in detail, andthereafter, external read-out of data will be described.

FIG. 5 is a diagram showing an example of an operation sequence forstoring 4-level data in memory cells. In data writing, 16-bit data issuccessively supplied externally. Address bit AA [2] externally supplieddesignates whether the supplied 16-bit data is upper data (word) orlower data (word) of the 32-bit data of the write-in unit. When externaladdress bit AA [2] is “0,” the lower 16-bit word is designated and whenexternal address bit AA [2] is “1,” the upper 16-bit word is designated.The identification of the upper word UW or the lower word LW is requiredonly in writing data into page buffer 6. Writing of data in memory cellarray 10 and verification read-out are performed in 16-bit units andtherefore the address bit AA[2] is not utilized in identification ofupper word UW and lower word LW. When data is read out externally,address bit AA [2] externally supplied is utilized for identificationbetween the upper word data and the lower word-data.

Two words having different values of external address bit AA [2]supplied externally via pads are written in page buffer 6 after thepositions of the two-word data bits are changed in data conversioncircuit 8 shown in FIG. 4. In this conversion of the data bit positionsin writing into page buffer 6, these bit positions are changed such thatdata bits at symmetrical positions in the lower byte and in the upperbyte are written in the same memory cells.

According to such change in bit positions of the words UW and LW, whenreading out, for example, 1 external word from the page buffer, read-outoperation from the page buffer is performed twice and thereby 16-bitdata or 16-bit external word, can be read out internally, and in datawriting into 1 memory cell, 2 bits of the same external data word can becompressed to be written into the same memory cell. In addition, the SLCconfiguration can be accommodated only by utilizing either region, lowerword LW or upper word UW in the page buffer.

Here, for aligning the corresponding bits of the same word, the adjacentdata terminals, or data bits D [0] and D [1], may be aligned. In thiscase, a semiconductor memory device can be implemented by which write-inand read-out of external data are performed in a byte mode.

Transformation of word and bit positions in data conversion circuit 8 aswell as write-in to page buffer 6 are repeatedly performed on 32 wordsexternally supplied. Then, 32-bit data is compressed to 16-bit data tobe written in memory cell array 10 via write driver 9 in data conversioncircuit 8. Before the write-in, first, the verification operation isperformed so that coincidence or non-coincidence between the data storedin the memory cells and the data stored in the page buffer is verified.Programming is performed, in accordance with new write data, only onmemory cells that require the programming operation, to reduce thecurrent consumption.

Data read out from memory cell array 10 is performed in accordance withthe serial sense scheme in which the sensing operation is successivelyperformed twice on a selected memory cell; In the first sensing, thelower byte data of each word is read out and at the time of the secondsensing operation, the upper byte data of each word is read out.Coincidence or non-coincidence between the data read out from the memorycell array 10 and the data read out from page buffer 6 is verified inverification circuit 5 shown in FIG. 4. When non-coincidence isdetected, data is again written in memory cell array 10 via write driver9 through data conversion circuit 8.

In the verification operation, verification circuit 5 stores the bitindicating the write-in completion at a corresponding position in pagebuffer 6 for each data bit. Thus, write-in can be performed again on thedata bits other than the normally written bits in each word. Write-in topage buffer 6, write-in (programming) to memory cell array 10 andverification are repeatedly performed by updating the addressessequentially for the internal 16 words and when the data write-in iscompleted precisely for all the internal 16 words, the write-in of dataof 32 words externally supplied is completed. Data writing in units ofthe internal 16 words is performed and the address generation sequencein the data writing and verification can be facilitated, andaccordingly, the configuration of the address generation part can besimplified.

FIG. 6 is a diagram schematically showing the flow of data. As shown inFIG. 6, lower word LW and upper word UW are sequentially supplied. Inthe data conversion circuit, these sequentially supplied 16-bit words LWand UW are changed in their positions and are stored in the page bufferas 32-bit data. For each 32-bit data of 2 words stored in this pagebuffer, upper word UW and lower word LW are compressed by the dataconversion circuit into 8-bit data, respectively, to be transmitted tomemory cell array 10 via the write driver as 16-bit memory cell data. Inmemory cell array 10, the lower word data and upper word data arerespectively stored as the upper byte data and the lower byte data inthe designated address of the block designated by address bit AA [23]between blocks BAL0 and BAL1 in the selected memory block BAL.

In data writing and verification operation, 8-bit data LW and UW writtenin this selected block BAL are read out in parallel and the verificationoperation and the rewriting are performed. In the data read-out, theregion BAL1 that corresponds to the upper logic address space and BAL0that corresponds to the lower logic address space in this block BAL areselected by internal address bit AE [2] (external address bit AA [23]).In the internal reading-out for the verification, the address bit-AA [2]is not utilized. The verification operation is performed in 2-word (32bits) units. In the external data read-out, the final 16-bit data D isgenerated and externally read out in accordance with internal addressbit AE [23] that corresponds to address bit AA [2].

Since the upper word and the lower word are stored in 16-bit memorycells, it is necessary to normally, externally apply the upper data(upper word) and the lower data (lower word) alternately, and it isnecessary to normally toggle the external address bit AA [2].

FIG. 7 is a diagram showing an example of an alteration sequence of theinputted address in the data writing. In FIG. 7, the sequence of theaddress alteration in the case when the starting address is an externaladdress AA [24′h000000] as an example. Here in FIG. 7, “24′” indicates24-bit signal/data and “h” indicates a hexadecimal notation. Inaddition, in FIG. 7 “1′b” indicates 1-bit signal and in the same manner“23′” indicates a 23-bit signal.

In FIG. 7, command “16′h00e8” is provided instructing data writing inthe first cycle. The command is typically transferred using a data bus.Subsequently, write-in data is transferred together with an addresssignal from the next cycle. When external address bit AA [2] is 0, thelower word data is latched and when the subsequently supplied addressbit AA [2] is “1,” the upper word data and the lower word data of 32bits are simultaneously written in the page buffer (data positionalteration is performed).

Thereafter, external address bit AA [2] is sequentially toggled and theremaining external address bits AA [23:3, 1:0] are sequentiallyincremented to be supplied together with the write-in data. When 32words are supplied, one write-in unit is completed. The data write-in isperformed in units of 32 words. Address bit AA [2] is not particularlyrequired to be always toggled by a-device that makes an access to thisnonvolatile semiconductor memory device. The device that accessesnonvolatile semiconductor memory device 1 may sequentially increment theaddress signal and the lowest address bit AA [0] may be switched toaddress bit AA [2] inside the semiconductor memory device 1. In thisnonvolatile semiconductor memory device, the write-in address to memorycell array 10 is incremented by 1 for the write-in data in the case whenexternal address bits AA [23:3, 1:0] are incremented by 1 address foreach 2 cycles.

FIG. 8 is a diagram schematically showing an example of theconfiguration of page buffer 6 shown in FIG. 4. In FIG. 8, page buffer 6includes a page buffer array 12 for storing write-in data andverification expected value data; a page buffer write-in/read-outcircuit 16 for writing data DIN [15:0] and DIN [31:16] in the pagebuffer array and for reading out data PBD [15:0] and PBD [31:16] frompage buffer array 12; and a word line selection circuit 14 for selectinga word line in the page buffer array 12. Page buffer array 12 is formedof an SRAM array in which SRAM cells are arranged in 32 rows and 64columns and 32 word lines WL and 64 pairs of bit lines BL are arranged.

As described later, word line selection circuit 14 selects one word linefrom among 32 word lines WL in accordance with word line pre-decodedsignals RAL, RAM and RAU generated by pre-decoding a page buffer addressPA [13:4], which in turn is generated on the basis of write-in addressAO [4:3,1:0] in writing. Upon word line selection, external address bitAA [2] is not utilized in the MLC configuration (this configuration isdescribed later).

Page buffer write-in/read-out circuit 16 can be set to 32-bit datawrite-in/read-out or to 16-bit data write-in/read-out set by means ofmetal slice. When page buffer write-in/read-out circuit 16 is set to the16 bit configuration, this semiconductor memory device operates in theSLC configuration, and in the case where the circuit 6 is set to the 32bit configuration, this semiconductor memory device operates in the MLCconfiguration.

Data DIN [31:16] and DIN [15:0] supplied to page bufferwrite-in/read-out circuit 16 is supplied by data conversion circuit 8shown in FIG. 4.

FIG. 9 is a diagram schematically showing the configuration of pagebuffer array 12 shown in FIG. 8. In FIG. 9, page buffer array 12includes SRAM cells 30 arranged in 32 rows by 64 columns. Word lines WL[31:0] are provided corresponding to the respective rows of SRAM cells30 and bit line pairs BL [63:0] and IBL [63:0] are providedcorresponding to the respective columns of SRAM cells 30. Bit lines BL[i] and IBL [i] are provided in pair so as to transfer complementarydata. Here “i” is an any integer ranging from 0 to 63.

An SRAM cell 30 includes inverters 30 a and 30 b forming a latch circuitfor storing data, and transfer gates 30 c and 30 d for connecting inputnodes of inverters 30 a and 30 b to corresponding bit lines BL [k] andIBL [k] in response to the signal on a corresponding word line WL [j].

Page buffer array 12 further includes, as bit line peripheral circuitry:a bit line precharging circuit 20 for precharging bit lines IBL [63:0]to the power supply voltage level in accordance with a complementary bitline precharging signal IPCIBL; a bit line precharging circuit 22 forprecharging bit lines BL [63:0] to the power supply voltage Vdd level inaccordance with a bit line precharging signal IPCBL; a bit line clearingcircuit 24 for discharging complementary bit lines IBL [63:0] to theground voltage level in accordance with a data clearing signal DCLR; anda bit line setting circuit 26 for setting bit lines BL [63:0] to theground voltage level in accordance with a data setting signal DSET.

Bit line precharging circuits 20 and 22 are formed of P-channel MOStransistors 20 a and 22 a having gates receiving bit line prechargingsignals IPCIBL and IPCBL, respectively. Bit line clearing circuit 24 isformed of an N-channel MOS transistor 24 a that is made conductive inaccordance with data clearing signal DCLR. Bit line setting circuit 26includes an N-channel MOS transistor 26 a rendered conductive todischarge bit lines BL [63:0] to the ground voltage level in accordancewith data setting signal DSET.

All bit lines IBL [63:0] and BL [63:0] are precharged to the commonpower supply voltage Vdd level in the bit line precharging circuits 20and 22 and all bit lines IBL [63:0] and BL [63:0] are simultaneously setto the ground voltage level in accordance with clearing signal DCLR anddata setting signal DSET by bit line resetting circuit 24 and in bitline setting circuit 26. These MOS transistors 20 a, 24 a and 26 a maybe provided in common to all bit lines IBL [63:0], or may be providedindividually to each bit line.

A bit line clearing circuit 24 a and a bit line setting circuit 26 a areprovided in the bit line peripheral circuitry and thereby resetting andsetting of the page buffer are collectively performed on the memorycells in page buffer array 12.

One word line is selected in accordance with an externally suppliedaddress supplied from among 32 word lines WL [31:0] and 32 pairs of bitlines are selected from among the 64 pairs of bit lines and datawriting/reading is performed.

FIG. 10 is a diagram showing a configuration of the part for generatingthe control signals to the page buffer array shown in FIG. 9. Thiscircuit for generating the control signals to the page buffer arrayshown in FIG. 10 is included in page buffer control circuit 7 shown inFIG. 4.

In FIG. 10, page buffer control circuit 7 includes: a delay circuit 50for delaying a page buffer read-out instruction signal CHPBR by apredetermined period of time; an inverter 51 for inverting a data setupinstruction signal CDSETUP that instructs the storage of write-in datain the page buffer; a NAND gate 53 for receiving an output signal ofdelay circuit 50, page buffer read-out instruction signal CBPBR andoutput signal CIDSETUP of inverter 51 to generate a page buffer read-outcontrol signal CLPBR; a delay circuit 54 for delaying data setupinstruction signal CDSETUP by a predetermined period of time; a metalswitch 55 for selecting either the output signal of delay circuit 54 ordata setup instruction signal CDSETUP by means of a metalinterconnection; an OR circuit 56 receiving an operation bank pointerenabling signal OBPE that designates the bank in the operation state andan output signal S1 of metal switch 55; an AND circuit 57 that receivesan output signal S2 of OR circuit 56 and output signal S1 of metalswitch 55 to generate a data setup permitting signal SETUP_MLC forpermitting data writing into the page buffer; an inverter 58 forreceiving internal address bit AO [2]; a NAND gate 59 that receives theoutput signal of inverter 58 and data setup permitting signal SETUP_MLC;and a metal switch that selects either the output signal of NAND gate 59or the power supply voltage and 60 for generating an MLC mode arrayselection signal MLC_SEL permitting data write-in to the page buffer ofthe corresponding bank.

This nonvolatile semiconductor memory device has a multi bankconfiguration and a page buffer and a page buffer control circuit areprovided to each bank and operation bank pointer enabling signal OBTEattains an H level when a corresponding bank is in the active state topermit an access to the page buffer, and in addition, the externalread-out of the data in the memory cell array is designated. In theoperation for writing data in the page buffer, operation bank pointerenabling signal OBPE is set at an L level and the data writing to thepage buffer for a corresponding bank is performed while data setupinstruction signal CDSETUP is at H level.

When operation bank pointer enabling signal OBPE is at the L level, thestorage data of the page buffer can also be read out externally.Accordingly, in the data writing into the memory cell array, thecorresponding operation bank pointer enabling signal OBPE is set at theH level. The write-in of the program data to the page buffer isperformed when no access is made to the corresponding bank. Programaddress bit AO [2] corresponds to external address bit AA [2].

Metal switch 55 selects the output signal of delay circuit 54 in the SLCconfiguration and selects data setup instruction signal CDSETUP in theMLC configuration. Metal switch 60 selects the power supply voltage Vddin the SLC configuration and selects the output signal of NAND circuit59 in the MLC configuration.

Control circuit 7 further includes: a delay circuit 61 for delaying adata load instruction signal CLOADW by a predetermined period of time; aNOR gate 62 for receiving an output signal of delay circuit 61 and adata load instruction signal CLOADW to generate a data load controlsignal ILOAD; a delay circuit 63 for delaying a timing signal TXLATD_PBgenerated in accordance with a transition in the address signal (clocksignal) by a predetermined period of time in internal read-out of data;a NAND gate 64 that receives an output signal S3 of delay circuit 63 andtiming signal TXLATD_PB; a gate circuit 65 that receives MLC selectionsignal MLC_SEL from metal switch 60 and data load control signal ILOAD;and a NOR gate 66 that receives the output signal of NAND gate 64 andpage buffer read-out control signal CLPBR from NAND gate 53.

Delay circuit 61 and NOR gate 62 form a fall delay circuit thatgenerates a one-shot pulse signal falling to the L level upon rise ofdata load instruction signal CLOADW to the H level and the rising ofthis one-shot pulse signal is set to the timing after elapse of thedelay time determined by delay circuit 51 since the fall of data loadinstruction signal CLOADW. Delay circuit 63 and NAND gate 64 also form aone-shot pulse generation circuit which generates a one-shot pulsesignal falling to the L level with a delay to the rising point of timingsignal TXLATD_PB.

Page buffer control circuit 7 further includes a composite gate 70 thatreceives the ground voltage and the output signal of inverter 69receiving the ground voltage and page buffer precharge control signalPBPRCG. A test mode instruction signal is typically supplied to inverter69 and the input signal of this inverter 69 is fixed at the L level inthe normal operation mode. Similarly, another test mode instructionsignal is supplied in place of the ground voltage in another test mode,and this test mode instruction signal is also fixed at the groundvoltage level in the normal operation mode. Accordingly, this compositegate 70 operates as an inverter that inverts page buffer prechargecontrol signal PBPRCG in the normal operation mode.

Page buffer control circuit 7 further includes a gate circuit 71 thatreceives a page buffer read-out instruction signal CHPBR, a data setupinstruction signal CDSETUP and a data ready instruction signal CRDY; aNOR gate 72 that receives data setup instruction signal CDSETUP, dataready instruction signal CRDY and the output signal of composite gate70; a NOR gate 73 that receives the output signal of gate circuit 71 andthe output signal of NOR gate 72; a composite gate 67 that receives theoutput signal of gate circuit 65 and an output signal of NOR gate 66; aNOR circuit 73 that receives the output signals of gate circuit 71 andNOR gate 72; and a NAND circuit 68 that receives an output signal of NORcircuit 73 and an output signal of composite gate 67.

Composite gate 67 is equivalently formed of an AND gate receiving datasetup instruction signal CDSETUP and the output signal of gate circuit65, and a NOR gate receiving the output signal of NOR gate 66 and theoutput signal of that AND gate. Gate circuit 71 generates a signal atthe H level when page buffer read-out instruction signal CHPBR is at theL level, data setup instruction signal CDSETUP is at the L level anddata ready instruction signal CRDY is at the H level.

Page buffer control circuit 7 further includes a delay circuit 74 fordelaying page buffer clear instruction signal CCLRPB by a predeterminedperiod of time; a NOR circuit 75 that receives an output signal of delaycircuit 74 and page buffer clear instruction signal CCLRPB; an inverter76 for inverting an output signal of NOR circuit 75; an inverter 77 thatreceives page buffer data set control signal PBDSET; a composite gatecircuit 78 that receives an output signal of NAND circuit 68, the outputsignal of NOR circuit 75 and page buffer data set control signal BPDSET;a composite gate circuit 79 that receives the output signal of NANDcircuit 68, the output signal of inverter 76 and the output signal ofinverter 77; an inverter 80 that receives page buffer data set controlsignal BPDSET; a NAND circuit 81 that receives the output signal ofinverter 80 and the output signal of inverter 76; a NAND circuit 82 thatreceives page buffer data set control signal PBDSET and an output signalof inverter 76; an inverter 13 that receives the output signal ofcomposite gate 78 to generate complementary bit line-prechargeinstruction signal IPCIBL; an inverter 84 that inverts the output signalof composite gate circuit 79 to generate bit line precharge instructionsignal IPCBL; an inverter 85 that inverts the output signal of NANDcircuit 81 so as to generate data clearing signal DCLR; and an inverter86 that inverts an output signal of NAND circuit 84 to generate data setinstruction signal DSET.

Composite gate 78 equivalently includes: a first AND gate that receivesthe output signal of NAND circuit 68 and the output signal of NORcircuit 75; and a second AND gate that receives the output signal of thefirst AND gate and page buffer data set instruction signal PBDSET.Composite gate circuit 79 equivalently includes: an OR gate thatreceives the output signal of NAND circuit 68 and the output signal ofinverter 76; and an AND gate that receives the output signal of this ORgate and the output signal of inverter 77.

Operation mode instruction signals CHPBR, CCLRPB and CDSETUP are signalsset, from command user interface (CUI) 2 shown in FIG. 4, in accordancewith an operation mode. Control signals PBDSET and PBPRCG are generatedin each operation cycle in accordance with the clock signal from theoscillation circuit within the page buffer control circuit describedlater.

In the operation mode of writing multi-level data in a memory cell, datasetup instruction signal CDSETUP is at the H level and operation bankpointer enabling signal OBPE is at the L level when writing data in thepage buffer to set up the write-in data. Accordingly, the output signalof OR circuit 56 is at the H level, the output signal from metal switch55 is also at the H level and data setup instruction signal SETUP_MLCfrom AND circuit 57 is at the H level. Accordingly, each time addressbit AO [2] attains “0” (L level), MLC mode array selection signalMLC_SEL outputted by NAND circuit 59 attains the L level.

In storage of write-in data in the page buffer, data setup instructionsignal CDSETUP is at the H level and therefore, the output signal ofcomposite gate circuit 67 is at the L level, and -responsively, theoutput signal of NAND circuit 68 is at the H level. Page buffer clearinstruction signal CCLRB is at the L level and the output signal of NORcircuit 75 is at the H level. In addition, page buffer data set controlsignal PBDSET is also at the L level. Accordingly, bit line prechargeinstruction signals IPCIBL and IPCBL turn L level when the address bitAO [2] attains “0”, and the bit lines are precharged in the page buffer.

When operation bank pointer enabling signal OBPE is at the L level anddata setup instruction signal CDSETUP is at the L level, the outputsignal of AND circuit 57 is at the L level and MLC mode array selectionsignal MLC_SEL is fixed at the H level. In this state, bit lineprecharge instruction signals IPCIBL and IPCBL are set at the L level inaccordance with timing signal TXLATD_PB generated according to theoperation mode. This is because, in read-out of the page buffer data,page buffer read-out instruction signal CHPBR is at the H level and thesignal CLPBR is set at the L level for a predetermined period of time.

When write-in data is present or data to be written is present in theverification operation, data ready signal CRDY is set at the H level. Inthis state, bit line precharge instruction signals IPCIBL and IPCBL areselectively activated in accordance with the output signal of NOR gatecircuit 73.

When precharge control signal PBPRCG is at the H level, bit lineprecharge instruction signals IPCIBL and IPCBL are selectively activatedthrough the route of NOR gate circuits 72, 73 and NAND circuit 68.

Where the whole of storage contents of the page buffer is to be reset,page buffer clear control signal CCLRPB is activated. Accordingly, theoutput signal of NOR circuit 75 turns L level and the output signal ofinverter 76 turns H level. At this time, page buffer data set controlsignal PBDSET is at the L level and bit line precharge instructionsignal IPCIBL attains the H level and complementary bit line prechargeinstruction signal IPCBL attains the H level. Moreover, the outputsignal IDCLR of NAND circuit 81 attains the L level and responsively,data clear instruction signal DCLR turns H level. Data set instructionsignal DSET is at the L level.

Page buffer data set instruction signal PBDSET is set at the H level,data clear instruction signal CCLRPB is at the L level, the outputsignal of NOR circuit 75 is at the H level, and the output signal ofinverter 76 is at the L level. In this state, complementary bit lineprecharge instruction signal IPCIBL from inverter 83 attains the L leveland bit line precharge instruction signal IPCBL attains the H level.Data clear instruction signal DCLR is at the L level and data setinstruction signal DSET attains the H level because the output signal ofinverter 76 is at the L level.

FIG. 11 shows, in a list form, the relation between an operation modesand the logic levels of the control signals to the page buffer bit lineperipheral circuitry. The precharging mode indicates the operation whenthe precharging operation is instructed and indicates standby state inthe data write-in, data read-out and data access to the page buffer. Inthe data setting and data clearing, all the word lines are driven to theselected state in the page buffer and the data setting and the dataclearing are performed on the whole memory cells of the page buffer.

By utilizing the configuration of this page buffer control circuit 7,the page buffer array can be precharged in accordance with the addressbit AO [2] in the data writing into the memory cell array and accuratedata writing can be achieved only in the data writing. In addition,selective data writing/reading can be performed on this page buffer inaccordance with control signal CHPBR.

FIG. 12 is a diagram schematically showing the configuration of theaddress conversion part included in page buffer control circuit 7 shownin FIG. 4. In FIG. 12, page buffer control circuit 7 includes: aninverter 89 that receives the output signal S2 of OR gate circuit 56shown in FIG. 10; a NAND gate circuit 90 that receives 7-bit address AA[6:0] externally supplied and the output signal of inverter 89; a metalswitch 91 for selecting either control signal S2 shown in FIG. 10 ordata setup permission instruction signal SETUP_MLC from the AND circuitshown in FIG. 10; a metal switch 92 for selecting either internaladdress signal AO [6:0] or [00, AO [4:3], AO [1:0], 1]; a NAND gatecircuit 95 that receives the output signals of the metal switches 91 and92; a gate circuit 93 that receives control signals S1 and S2; a metalswitch 94 for selecting either the output signal of gate circuit 93 orthe ground voltage (“0”); and a NAND gate circuit 96 that receives theoutput signal of metal switch 94 and 7-bit address [00A [3:0] 1].

Metal switch 91 selects MLC data setup permission instruction signalSETUP_MLC in the MLC configuration and metal switch 92 selects 7-bitaddress [00AO [4:3], AO [1:0]1] in the MLC configuration. Metal switch94 selects the output signal of gate circuit 93 in the MLCconfiguration. The gate circuit 93 outputs a signal of the H level whenoutput control signal S1 is at the L level and output control signal S2is at the H level.

NAND gate circuits 90, 95 and 96 each operate as an inverter whenenabled, to invert the received 7-bit address to generate selected 7-bitaddress [6:0].

Page buffer control circuit 7 further includes: a NAND gate circuit 97that receives the output signals of NAND gate circuits 90, 95 and 96 togenerate a complementary 14-bit write-in address signal; and an inverter98 that receives the output signal of NAND gate circuit 97 so as togenerate complementary 14-bit address signals PA [12:0], [13:12]. Here,symbol PA [13:0:2] indicates the formation of seven pairs ofcomplementary signals in 2-bit units from the complementary signalsgenerated from each bit of P [6:0].

Page buffer control circuit 7 further includes: a word line predecoder99 that pre-decodes complementary internal address signal PA [13:4] frominverter 98 to generate word line pre-decoded signals RAU [1:0], RAM[3:0] and RAL [3:0] for designating a word line of the page buffer; ametal switch 100 for selecting either complementary internal addresssignal PA [1:0] or the logic “1” (power supply voltage Vdd level); and abit line predecoder 101 that pre-decodes complementary internal addresssignal PA [3:2] and the address bit from metal switch 10 so as togenerate a bit line selecting signal Y [3:0].

Word line predecoder 99 carries out the pre-decoding operation at thetime of the activation of word line selection signal IWL_SEN, and drivesall the pre-decoded signals to the selected state at the time of theactivation of page buffer word line clear instruction signal CLRPBWLactivated in data clearing.

Word line pre-decoding signal RAU [1:0] is generated on the basis ofinternal address bits PA [13:12] and word line pre-decoded signal RAM[3:0] is generated on the basis of complementary internal addresssignals PA [11:8]. Word line pre-decoding signal RAL [3:0] is generatedon the basis of complementary internal address signal PA [7:4]. In eachof these pre-decoded signals RAU [1:0], RAM [3:0] and RAL [3:0], onesignal is driven to the selected state.

Bit line predecoder 101 performs the pre-decoding operation inaccordance with complementary internal address signals PA [3:2] in theMLC configuration, drives 2-bit bit line selection signal in 4-bit bitline selection signal Y [3:0] to the selected state to select thirty-twopairs of bit lines to transfer 32-bit data. In the SLC configuration,one-bit bit line selection signal in four-bit bit line selection signalY [3:0] is driven to the selected state in accordance with complementaryinternal address signals PA [3:0]. Accordingly, in this case, ¼selection is carried out on sixty-four pairs of bit lines and thus,sixteen pairs of bit lines are selected.

As for word lines, ½ selection is effected by the pre-decoded signal RAU[1:0] and ¼ selection is effected in each of pre-decoded signals RAM[3:0] and RAL [3:0], and in total, 1/32 selection is effected on entireword lines and as a result, one word line in thirty-two word lines WL[31:0] is driven to the selected state.

By way of example, the page buffer has a hierarchical word lineconfiguration and includes four main word lines and eight sub word linesarranged corresponding to each main word line. One main word line isselected in accordance with pre-decoded signal RAL [3:0] and one subword line in eight sub word lines is selected in accordance withpre-decoded signals RAU [1:0] and RAM [3:0].

In writing data in a memory cell, control signals S1 and S2 are both setat the H level as shown in FIG. 10. In this condition, all bits of theoutput signal of NAND gate circuit 90 are at the H level. The outputsignal of NAND gate 93 is at the L level and the output signal of NANDgate circuit 96 is also at the H level (for 7 bits). Accordingly, NANDgate circuit 97 selects address bits [00, AO [4:3], AO [1:0], 1] fromNAND gate circuit 95 to generate complementary internal address signalPA [13:0:2] of 14 bits in accordance with the selected address bits. Inthe MLC configuration, address bit AO [2] is not utilized. Specifically,even if data writing and data reading are performed on the page buffer,data write-in/read-out is performed to the region designated by addressbits AO [4:3] and AO [1:0]. In this case, a word line and a bit line areselected in accordance with 4-bit address and therefore, a region havingthe total of sixteen addresses is designated and 2-word data of 32 bitsexternally supplied is sequentially stored in sixteen successiveaddresses of the page buffer, respectively.

When the operation bank pointer enabling signal (see FIG. 10) is at theH level, the control signal S2 is at the H level. In this state, whencontrol signal S1, or data setup instruction signal CDSETUP is at the Llevel, the output signal of gate circuit 93 is at the H level andcomplementary internal address PA [13:0:2] is generated by NAND gatecircuit 96 in accordance with address bits [00AO [3:0] 1]. In this case,data writing into the page buffer is performed in accordance withaddress bits AO [3:0]. Write-in of data to a memory cell array is notperformed and therefore, an address region in the page buffer is simplydesignated even when address bit AO [2] is used and therefore, noparticular problem arises since there is no need to identify the upperdata and the lower data. In this case, external 16-bit word data issequentially stored in the page buffer.

When operation bank pointer enabling signal OBPE is at the L level andcontrol signal S1 is at the L level, control signal S2 is at the Llevel. In this state, complementary internal address signal PA [13:0:2]is generated by NAND gate circuit 90 in accordance with external addressAA [6:0] and data read-out from the page buffer is performed.

As shown in FIG. 12, in writing the data into a memory cell, an internaladdress excluding the address bit AO [2] corresponding to externaladdress signal bit AA [2] is generated by metal switch 92 and thereby,at the time of the MLC configuration, data write-in to the page bufferand to the memory cell can be performed with address bit AA [2] beingused for the identification of the upper or lower word data of 32-bitdata (write-in address of the page buffer is equal to the write-inaddress of the memory cell).

FIG. 13 is a diagram showing the configuration of the part thatgenerates word line selection activation signal IWL_SEL supplied to wordline predecoder 99 shown in FIG. 12. Word line selection activationsignal IWL_SEL is also generated by page buffer control circuit 7 shownin FIG. 4.

In FIG. 13, page buffer control circuit 7 includes a three-input NORgate circuit 101 that receives timing signal TXLATD_PB indicating atransition in the page buffer address, control signal S3 shown in FIG. 4and page buffer read-out control signal CLPBR shown in FIG. 4; a delaycircuit 102 for delaying page buffer write-in signal PBWRT defining datawrite-in timing to the page buffer-by a predetermined period of time; aNAND gate circuit 104 that receives delay page buffer write-in controlsignal DPBWRT from delay circuit 102 and page buffer load control signalPBLOAD instructing data load to the page buffer; a NOR gate circuit 105that receives the output signals of NOR gate circuit 101 and AND gatecircuit 104; a delay circuit 103 for delaying page buffer read-outcontrol signal PBREAD that controls the timing of data read-out from thepage buffer by a predetermined period of time; a NOR gate circuit 106that receives the output signal of delay circuit 103 and data loadinstruction signal LOADW permitting data load to the page buffer; a NANDgate circuit 107 that receives the output signals of NOR gate circuits105 and 106; and a NAND gate circuit 108 that receives the output signalof NAND gate circuit 107 and MLC selection signal MLC_SEL to generateword line selection activation signal IWL_SEL.

Control signals PBWRT, PBLOAD and PBREAD each are a control signal thatdefines the data write timing to the page buffer and are generated inOSC circuit 3 shown in FIG. 4. Data load instruction signal LOADW is asignal instructing the permission of data loading and is applied fromcommand user interface circuit 2.

When page buffer write-in control signal and page buffer load controlsignal PBLOAD both attain the H level, the output signal of AND gatecircuit 104 attains the H level. Responsively, the output signal of NANDgate circuit 107 attains the H level, and word line selection activationsignal IWL_SEL is driven to the active state at L level. In datareading-out from the page buffer (in the verification operation), whenpage buffer read-out control signal PBREAD attains the H level (loadpermission instruction signal LOADW is at the L level), the outputsignal of NOR gate circuit 106 attains the L level and word lineselection activation signal IWL_SEL is driven to the activated state.

Accordingly, upon data write-in to a memory cell and the verificationoperation utilizing the page buffer, write-in and read-out of data tothe page buffer are controlled in accordance with these control signalsPBWRT, PBLOAD and PBREAD. In only the read-out operation to the pagebuffer or only the write-in operation to the page buffer, MLC mode arrayselection signal MLC_SEL is set at the H level (independent of addressbit AO [2]) in accordance with operation bank pointer enabling signalOBPE and data setup instruction signal CDSETUP. Under such condition,upon data write-in, a word line selection is performed in accordancewith load instruction signal LOADW and data read-out is performed inaccordance with page buffer read-out control signal CLPBR. Upon dataread out, data read-out timing is set in accordance with timing controlsignal TXLATD_PB corresponding to the detection of a transition in theaddress signal (by creating timing that corresponds to the transition ofthe internal clock signal).

FIG. 14 is a diagram schematically showing the configuration of the partthat generates clear page buffer word line signal CLRPBWL shown in FIG.12. This part shown in FIG. 14 is included in page buffer controlcircuit 7. Page buffer control circuit 7 includes: a delay circuit 109for delaying page buffer clear instruction signal CCLRPB externallyapplied; and an AND gate circuit 110 that receives an output signal ofdelay circuit 109 and page buffer clear instruction signal CCLRPB. Delaycircuit 109 and AND gate circuit 110 form a rise delay circuit and whenclear page buffer word line instruction signal CCLRPBWL outputted fromAND gate circuit 110 is activated to be at the H level, all the wordlines of the page buffer are simultaneously driven to the selectedstate, and the data stored in the page buffer is cleared.

FIG. 15 is a diagram schematically showing the part of word line drivecircuit 112 that is included in word line selection circuit 14 shown inFIG. 8. The word line drive circuit 112 drives one word line inthirty-two word lines WL [31:0] to the selected state in accordance withpre-decoded signals RAL [3:0], RAM [3:0] and RAU [1:0] of the addressgeneration circuit shown in FIG. 12. The word line drive circuit 112operates statically and drives a corresponding word line to the selectedstate in accordance with the supplied pre-decoded signals.

The word line drive circuit 112 includes four main word line selectionsignals and eight word line drivers arranged corresponding to each mainword line selection signal, although not particularly limited to sucharrangement. One of the four main word line selection signals is drivento the selected state in accordance with row address pre-decoded signalRAL [3:0]. One word line driver in eight word line drivers is driven tothe selected state in accordance with row pre-decoded signals RAM [3:0]and RAU [1:0]. The corresponding word line is driven to the selectedstate by the activated main word line selection signal and the selectedword line driver.

The word line drive circuit 112 is required to drive the word line tothe selected state in a static manner in accordance with the suppliedpre-decoded signals and the internal configuration thereof is notspecifically limited. The reason why word lines WL [31:0] are driven ina static manner is that page buffer 6 is formed of an SRAM andwrite-in/read-out to the page buffer in verification operation aresuccessively performed at high speed in accordance with the addresstransition (edge of the clock signal).

FIG. 16 is a diagram schematically showing the configuration of pagebuffer write-in/read-out circuit 16 shown in FIG. 8. In FIG. 16, thepage buffer write-in/read-out circuit includes a lower page buffersensing/driving circuit 120 that performs write-in and read-out of thelower 16-bit data DIN [15:0] and SADATA [15:0]; and an upper page buffersensing/driving circuit 122 that writes and reads the upper 16-bit dataDIN [31:16] and SDATA [31:16]. Data DIN [15:0] and data DIN [31:16] arewrite-in data to this page buffer while data SADATA [15:0] and dataSDATA [31:16] are read-out data from the page buffer.

Lower page buffer sensing/driving circuit 120 and upper page buffersensing/driving circuit 122 have the same configuration. Lower pagebuffer sensing/driving circuit 120 receives the output signal of metalswitch 125 for selecting either bit line selection signals of 4 bits Y[3:0] or [0,Y [2], 0,Y [0]] as a bit line selection signal and alsoreceives lower 16-bit data DIN [15:0] at data input DIN. In addition,lower page buffer sensing/driving circuit 120 receives sense amplifieractivation signal SAEN and inverted and delayed sense amplifieractivation signal ISAEN_D for data read-out and in addition, receivesbit line precharging instruction signal IPCIPL shown in FIG. 10 as aprecharging instruction signal IPC. Furthermore, lower page buffersensing/driving circuit 120 receives upper byte selection signalIDRVEN_U and lower byte selection signal IDRVEN_L, to perform datawriting in a byte unit. Data writing and reading can be performed in abyte unit for 16-bit words in accordance with the byte selection signalsIDRVEN_U and IDRVEN_L.

Upper page buffer sensing/driving circuit 122 receives, as a bit lineselection signal, the signal selected by metal switch 126 that selectseither 4-bit data of “0” or bit line selection signal [Y [3], 0,Y [1],0] of 4 bits. Data input DIN is supplied with upper 16-bit data DIN[31:16]. The sense amplifier activation signal input is supplied withthe output of metal switch 127 which selects either the sense amplifieractivation signal SAEN or the ground potential. The output signal ofmetal switch 128, which selects either 16-bit data of “1” or upper bytedata drive signal IDRVEN_U and IDRVEN_L, is supplied as a byte dataselection signal IDRVEN. The output signal of metal switch 129, whichselects either power supply voltage Vdd or precharging instructionsignal IPC (corresponding to bit line precharging instruction signalIPCBL), is supplied as a precharging instruction signal. Inverted anddelayed sense amplifier activation signal ISAEN_D is supplied as aninverted and delayed sense amplifier activation signal.

FIG. 16 shows the connection paths in metal switches 126 to 129established in the MLC configuration. Accordingly, in the SLCconfiguration, all the bits of the output signal of metal switch 126assume “0”, sense amplifier activation signal SAEN is set at the L level(ground voltage level) of the inactive state and a byte data selectionsignal in the inactive state is normally supplied as a data driveselection signal IDRVEN. In addition, precharging instruction signal IPCis normally maintained in the inactive state. Specifically, in the SLCconfiguration, the upper page buffer sensing/driving circuit 122 is notused while lower page bias sensing/driving circuit 120 is used to carryout write-in and read-out of 16-bit data.

This lower page buffer sensing/driving circuit 120 performs the bit lineselection operation in accordance with bit line selection signals Y [2]and Y [0] and upper page buffer sensing/driving circuit 122 performs thebit line selection operation in accordance with bit line selectionsignals Y [3] and Y [1]. In the MLC configuration, internal addresssignal PA [1:0] is set at “1.” Accordingly, bit line predecoder 101shown in FIG. 12 carries out the ½ selection operation to drive upperbit line selection signal Y [3:2] or lower bit line selection signal Y[1:0] to the selected state. Thus, bit line pairs of 16 bits areselected in each of lower page buffer sensing/driving circuit 120 andupper page buffer sensing/driving circuit 122, and write-in or read-outof data of 16 bits each, or the total of data of 32 bits, issimultaneously performed.

FIG. 17 is a diagram schematically showing the configurations of lowerpage buffer sensing/driving circuit 120 and upper page buffersensing/driving circuit 122 shown in FIG. 16. The lower page buffersensing/driving circuit 120 and upper page buffer sensing/drivingcircuit 122 have the same configuration and therefore, only theconfiguration of one of these circuits is shown in FIG. 17.

In FIG. 17, each of page buffer sensing/driving circuits 120 and 122includes: a 16-bit internal data bus 130; a multiplexer 131 forselecting bit line pairs BLP [15:0] in accordance with bit lineselection signal Y [0] and connecting the selected bit line pairs tointernal data bus 130; a multiplexer 132 for selecting bit line pairsBLP [31:16] in accordance with bit line selection signal Y [1] andconnecting the selected bit line pairs to internal data bus 130; amultiplexer 133 for selecting bit line pairs BLP [47:32] in accordancewith bit line selection signal Y [2] and connecting the selected bitline pairs to internal data bus 130; and a multiplexer 134 for selectingbit line pairs BLP [63:48] in accordance with bit line selection signalY [3] and connecting the selected bit line pairs to internal data bus130. Bit line pairs BLP [63:0] includes bit lines BL [63:0] and IBL[63:0].

Each of these page buffer sensing/driving circuits 120 and 122 furtherincludes: a PB write drive circuit 135 that is selectively activated inaccordance with inverted and delayed sense activation signal ISAEN_D aswell as data byte selection signals IDRVEN_U and IDRVEN_L, to drive,when activated, the selected bit line pairs via internal data bus 130 inaccordance with received 16-bit data DIN; and a PB sense circuit 136that is selectively activated in accordance with sense amplifieractivation signal SAEN as well as data byte selection signals IDRVEN_Uand IDRVEN_L to sense and amplify the data on internal data bus 130 togenerate 16-bit read-out data SADATA.

The activation and deactivation of PB sense circuit 136 and PB writedrive circuit 135 are controlled in units of bytes in accordance withdata byte selection signals IDRVEN_U and IDRVEN_L. In lower page buffersensing/driving circuit 120 in the MLC configuration, multiplexers 131and 133 performs the selection operations in accordance with bit lineselection signals Y [2] and Y [0], while multiplexers 132 and 134 remainnon-conductive. On the other hand, in upper page buffer sensing/drivingcircuit 122 in the MLC configuration, multiplexers 132 and 134 performthe selection operations in accordance with bit line selection signals Y[3] and Y [1].

Internal data bus 130 is precharged to a predetermined voltage level byprecharging circuit 137 that receives precharging signal IPCcorresponding to the bit line precharging instruction signal uponcompletion of the data write-in/read-out.

FIG. 18 is a diagram showing the configuration of the part thatgenerates sense amplifier activation signals SAEN and ISEN_D shown inFIG. 16. The configuration shown in this FIG. 18 is included in pagebuffer control circuit 7 shown in FIG. 4.

In FIG. 18, the page buffer sense amplifier control part in page buffercontrol circuit 7 includes: an inverter 140 that receives a data setupinstruction signal CDSETUP; a metal switch 141 for selecting either anoutput signal of inverter 140 or power supply voltage Vdd; an inverter142 that receives an access mode activation signal TXLCE; a NAND gatecircuit 143 that receives a page buffer read-out instruction signalCHPBR, an output signal of inverter 142 and an output signal of metalswitch 141; and a gate circuit 144 that receives an output signal ofNAND gate circuit 143 and data strobe control signal STRBW. This gatecircuit 144 outputs a signal of the H level when data strobe controlsignal STRBW is at the H level or the output signal of NAND gate circuit143 is at the L level.

The page buffer control part in page buffer control circuit 7 furtherincludes: a NAND gate circuit 145 that receives the output signal ofgate circuit 144 and bit line precharging instruction signal IPCBL; aninverter 146 that receives an output signal of NAND gate circuit 145 togenerate sense amplifier activation signal SAEN; and a delay circuit 147for generating inverted and delayed sense activation signal ISAEN_D bydelaying the output signal of NAND gate circuit 145 by a predeterminedperiod of time.

Metal switch 141 selects the output signal of inverter 140 in the MLCconfiguration. Data setup instruction signal CDSETUP is set at the Hlevel in data writing. Accordingly, in this case, the output signal ofNAND gate circuit 143 is fixed at the H level and activation andinactivation of sense amplifier activation signals SAEN and ISAEN_D areeffected in accordance with strobe timing control signal STRBW. Strobetiming control signal STRBW is activated at a predetermined timing inaccordance with the clock signal internally generated in data read-outfrom the page buffer.

In the case where the data is read out externally from the page buffer,page buffer read-out instruction signal CHPBR is set at the H level. Inthis state, if the page buffer corresponding to the corresponding bankis permitted to operate, access enabling signal TXLCE is set at the Llevel (generated on the basis of the bank operating pointer). Therefore,in this condition, the output signal of NAND gate circuit 143 is at theL level and responsively, the output signal of OR gate circuit 144 is atthe H level. When bit line precharging instruction signal IPCLBL changesfrom the L level to the H level and the precharging of the page bufferbit line and the internal data line completes, sense amplifieractivation signal SAEL is activated. In data writing to the page buffer,page buffer read-out instruction signal CHPBR is at the L level, senseamplifier activation signal SAEN is fixed at the L level, inverted anddelayed sense amplifier activation signal SISAEN_D from delay circuit147 is in the active state and data writing to the page buffer isperformed in accordance with strobe timing control signal STRBW.

FIG. 19 is a diagram showing the configuration of the portion thatgenerates byte selection signals IDRVEN_U and IDRVEN_L shown in FIG. 16.The circuit shown in this FIG. 19 is also included in page buffercontrol circuit 7 shown in FIG. 4.

In FIG. 19, page buffer control circuit 7 includes: a NOR gate circuit150 that receives data ready instruction signal CRDY and data setupinstruction signal CDSETUP; a NOR gate circuit 151 that receives theoutput signal of NOR gate circuit 150 and byte mode instruction signalTXLBYTE; and a gate circuit 152 that receives NOR gate circuit 151 andword mode instruction signal TMS_X16LOAD. This byte mode instructionsignal TXLBYTE indicates whether data writing to the page buffer isperformed in byte mode and when it is set at the L level, data writingto the page buffer is performed in byte mode. Word mode instructionsignal TMX_X16LOAD indicates data writing in a word unit and when it isset at the H level, data writing is performed in a word unit. Gatecircuit 152 outputs a signal at the H level when the output signal ofNOR gate circuit 151 is at the L level or word mode instruction signalTMS_X16LOAD is at the H level.

Page buffer control circuit 7 further includes: a NOR gate circuit 155that receives upper/lower byte instruction signal BXHLB and the outputsignal of gate circuit 152; a NOR gate circuit 153 that receives dataload instruction signal LOADW and page buffer write in control signalPBWRT to generate a drive enable signal IDRVEN; and a gate circuit 155that receives the output signal of gate circuit 152 and upper/lower byteinstruction signal BXHLB.

As shown in FIG. 13, data load instruction signal LOADW is activated fora predetermined period of time when data load instruction signal CLOADWis activated. Page buffer write-in control signal PBWRT is activated atthe time of data writing to the page buffer. Upper/lower byteinstruction signal BXHLB has the logic level set in accordance with anexternal signal and designates the lower byte data when set at the Hlevel, and designates the upper byte data when set at the L level.

Page buffer control circuit 7 further includes: NOR gate circuit 156that receives the output signal of NOR gate circuit 153 and the outputsignal of NOR gate circuit 154; a NOR gate circuit 157 that receives theoutput signal of NOR gate circuit 153 and the output signal of gatecircuit 155; a NAND gate circuit 158 that receives MLC selection signalMLC_SEL and the output signal of NOR gate circuit 156 to generate lowerbyte drive enable signal IDRVEN_L; a NAND gate circuit 159 that receivesMLC selection signal MLC_SEL and the output signal of NOR gate circuit157 to generate upper byte selection signal IDRVEN_U; a NAND circuit 160that receives the output signals of NAND gate circuits 158 and 159, dataclear signal IDCLR and data set signal IDSET; inverters 161 and 162cascaded in two stage and receiving the output signal of NAND gatecircuit 160; a NOR gate circuit 163 that receives the output signal ofNOR gate circuits 156 and 157; and a NOR gate circuit 164 that receivesthe output signal of NOR gate circuit 163 and MLC mode array selectionsignal MLC_SEL to generate a data take-in activation signal DRVEN_E.

Bit line load instruction signal IBLLOAD from inverter 162 is activatedwhen a data access is not performed on the page buffer. The bit lineload instruction signal IBLLOAD is activated in accordance with loadcontrol signal CLOAD that is activated in accordance with data loadinstruction signal-CLOADW shown in FIG. 13 in an operation modedifferent from the data setup.

Page buffer write instruction signal PBWRT is activated upon theverification operation.

In the MLC configuration, upper/lower byte data selection signal BXHLBis set at the H level and word mode instruction signal TMS_X16LOAD isalso set at the H level. Accordingly, the output signals of gatecircuits 154 and 155 are fixed at the L level. Drive activation signalIDRVEN for bit lines is activated in accordance with load instructionsignal LOADW or page buffer write-in instruction signal PBWRT. In datawriting to the page buffer, drive activation signal IDRVEN is activatedin accordance with data load instruction signal LOADW. In the MLCconfiguration, MLC mode array selection signal MLC_SEL attains the Hlevel when address bit AO [2] is “1” (see FIG. 10). Accordingly, bitline drive enable (byte selection signals) signals IDRVEN_L and IDRVEN_Uare activated to be at the L level when address bit AO [2] assumes “1.”In this state, data writing to the page buffer is performed.

On the other hand, drive enable signal DRVEN_E is set at the H level inaccordance with drive activation signal DRVEN, because MLC selectionsignal MLC_SEL is at the L level when address bit AO [2] is “0” as shownin FIG. 20. When address bit AO [2] is “1,” MLC mode array selectionsignal MLC_SEL is at the H level and drive activation signal DRVEN_E isset at the L level (active state). In other words, drive activationsignal DRVEN_E designates take-in/latching of the first data of twosuccessive 16-bit data and when the second data of the two successive16-bit data is applied, bit line drive enable signals (byte selectionsignals) IDRVEN_U and IDRVEN_L are activated and write-in to the pagebuffer is performed.

FIG. 21 is a diagram schematically showing the configuration of the partthat generates page buffer write-in data DIN [31:0] in data conversioncircuit 8 shown in FIG. 4. In FIG. 21, data conversion circuit 8includes: a NAND gate circuit 173 that receives drive activation signalDRVEN_E and data setup instruction signal CDSETUP; an inverter 174 thatreceives data latch-instruction signal MLC_LE; a NAND gate circuit 175that receives an output signal of NAND gate circuit 173 and an outputsignal of inverter 174; a metal switch 176 that selects either theoutput signal of NAND gate circuit 175 or power supply voltage Vdd; aregister circuit 178 responsive to the rise of the output signal ofmetal switch 176, for taking in and latching write-in data WD16 [15:0]externally applied; and a metal switch 177 that selects either powersupply voltage Vdd or write-in data WD16 [15:0] externally applied.

16-bit data DINB [15:8] and DIN [7:0] are generated by register circuit178 and 16-bit data DIN [31:24] and DINB [23:16] are generated by metalswitch 177. This metal switch 177 selects write-in data WD16 [15:0] inthe MLC configuration and selects power supply voltage Vdd in the SLCconfiguration.

To this register circuit 178, there are provided: a metal switch 170that receives either page buffer clear instruction signal CLRPB or theground voltage; an OR gate circuit 171 that receives an output signal ofmetal switch 170 and a main reset signal RMRST; and an inverter 172 thatreceives an output signal of OR gate circuit 171, to generate a resetsignal RSET. The storage data of register circuit 178 is reset inaccordance with reset signal RSET outputted by the inverter 172.

Data conversion circuit 8 further includes interconnection 180 thatconverts the order of arrangement of data DINB [15:0] and DINB [23:16]to data DINB [23:8] and DINB [8:23]; a metal switch 179 that selectseither the ground voltage or data setup instruction signal CDSETUP; aninverter 181 that receives the output signal of metal switch 179; and acomposite gate circuit 182 that selects either 16-bit data DINB [23:8]or DINB [8:23] in accordance with the output signal of inverter 181.

Metal switch 179 selects data setup instruction signal CDSETUP in theMLC configuration and selects the ground voltage in the SLCconfiguration. Composite gate circuit 182 selects data bits DINB [8:23]when the output signal of inverter 181 is at the L level and selects thedata bits [23:8] when the output signal of inverter 181 is at the Hlevel. Arrangement positions of bits are in reversed relation betweendata bits DINB [8:23] and data bits DINB [23:8].

In the programming operation, data setup instruction signal CDSETUP isset at the H level, data bits DINB [8:23] are selected and data DIN[23:16] and DINC [15:8] are generated. Metal switch 183 selects dataDINC [15:8] to generate data bits DIN [15:8] in the MLC configuration.Accordingly, in the MLC configuration, data bits DIN [23:8] areoutputted with the bit positions thereof being converted.

In data writing, data take-in activation signal (drive activationsignal) DRVEN_E is activated when the first write-in data is supplied(when address bit AO [2] is “0”) so that the output signal of NAND gatecircuit 173 turns L level and responsively, he output signal of NANDgate circuit 175 attains the H level and register circuit 173 takes inand stores write-in data WD16 [15:0] externally applied. Accordingly,the first data is stored in register circuit 178 and subsequentlysuccessive data is generated by metal switch 177 in accordance with thesuccessive external word data (upper word). When the second data issupplied, the data positions of 32-bit data are changed accordingly.

FIG. 22 is a diagram schematically illustrating the data bit positionconverting operation in data conversion circuit 8 shown in the aboveFIG. 21. Now, it is assumed that write-in data WD1 and WD2 aresequentially and successively supplied. The bit position orders of upperbyte data [15:8] of write-in data WD1 and lower byte data [7:0] ofwrite-in data WD2 are changed by composite logic gate circuit 182 shownin FIG. 21 and the data byte positions thereof are also changed.Accordingly, when 32-bit data is generated, the upper byte data ofwrite-in data WD2 turns write-in data DIN [31:24] to the page buffer,and the data having the bit positions of the upper byte data of write-indata WD1 changed turns write-in data DIN [23:16] to the page buffer. Inaddition, data [0:7] having the bit positions of lower byte data [7:0]of write-in data WD2 reversed turns write-in data DIN [15:8] to the pagebuffer. Lower byte data [7:0] of write-in data WD1 becomes write-in dataDIN [7:0] to the page buffer. Accordingly, this composite-logic gateachieves the change in the data bit positions upon writing into pagebuffer shown in FIG. 5.

FIG. 23 is a diagram schematically showing the configuration of the partthat generates write-in data to memory cells in data conversion circuit8 shown in FIG. 4. In FIG. 23, data conversion circuit 8 includes: aregister circuit 185 that takes in and latches 32-bit data PD32 [31:0]read out from the page buffer in accordance with data latch controlsignal PBLATCH; and a data compressing circuit 186 that receives 32-bitoutput data PD32A [31:16] and PD32A [15:0] of the register circuit 185as 16-bit data PD2 [15:0] and PD1 [15:0] respectively to compress thereceived data to 16-bit data WD [15:0] for outputting.

Register circuit 185 is formed of a latch circuit and enters a throughstate when latch instruction signal PBLATCH is at the L level and entersa latching state when latch instruction signal PBLATCH is at the Llevel. In addition, register circuit 185 has the storage data reset inaccordance with reset signal RSET.

The data degenerating circuit 186 processes the compression operation ofthe bits at corresponding positions in 16-bit data PD1 [15:0] and PD2[15:0]. FIG. 23 shows, as a representative, the configuration forgenerating 1-bit compressed data. Data compression circuit 186 includes:a NAND gate circuit 190 that receives inverted data bit IPD1 andinverted data bit IPD2; a NAND gate circuit 191 that receives inverteddata bit IPD1 and data bit PD2; a NAND gate circuit 192 that receivesdata bits PD1 and IPD2; a NAND gate circuit 193 that receives the outputsignals of these gate circuits 190 to 192; and an inverter 194 thatinverts the output signal of NAND gate circuit 193 so as to generate acompressed data bit. Inverted data bit IPD1 and IPD2 are inverted bitsof data bits PD1 and PD2, respectively.

In data compressing circuit 186 shown in FIG. 23, the compressed databit is set at the H level (“1”) when all of the output signals of NANDgate circuits 190 to 192 are at the H level. This condition is satisfiedwhen data bits PD1 and PD2 are both “1.” If at least one of data bitsPD1 and PD2 is “0,” the compressed data bit assumes “0” (L level).Accordingly, 2-bit data (1, 1) corresponds to the state of the H leveland the remaining 2-bit data (0, 0), (0, 1) and (1, 0) are madecorresponding to the state of storing data “0”.

Specifically, as shown in FIG. 24, the state where data bits (1, 1) arestored is made corresponding to the erased state and the states wheredata “10”, “01”, and “00” are stored are made corresponding to theprogrammed state.

Accordingly, in data writing, first, the erasure verification operationis performed before data writing to a memory cell, to compare thestorage data with write-in data. After the verification, if thethreshold voltage of the memory cell corresponds to the write-in data,the corresponding 2-bit data in the page buffer is changed to “11”.Subsequently, the programming operation increases the threshold voltagesby one value. In the verification operation, when the storage datacoincides with the write-in data, the bit is set to “1”. As a result,data writing is performed in accordance with the compressed data bitonly on the memory cells that requires further increase of the thresholdvoltage.

This data writing is simultaneously performed in units of 16 bits, andtherefore a high voltage is supplied to bit lines from the write driverso that the data writing is performed by the channel hot electrons(CHE). Data writing requires erasure and erasure verification beforewriting as well as a program verification operation, and in addition, itis necessary to adjust the program voltage of word lines upon writing,and these operations are simultaneously performed with 32-word data(16-word data for memory cells) being a unit. As a result, data can bewritten into 16 memory cells connected to the same word linesuccessively without changing the word line voltage once set andexternal 32-word data can be successively written. Further, theverification operation is performed in units of internal 16 words.

FIG. 25 is a diagram schematically showing the configuration of the partrelated to data program included in OSC circuit 3 and in the commanduser interface (CUI) shown in FIG. 4. In FIG. 25, OSC circuit 3includes: an oscillator 200 that oscillates in accordance withoscillation enable signal IOSCE and generates a clock signal of apredetermined period; and a program/verification control signalgeneration circuit 201 that generates control signals required for theprogramming and verification operations in accordance with the clocksignal outputted from oscillator 200. The generated control signalsinclude page buffer write-in control signal PBWRT, page buffer read-outcontrol signal PBREAD, page buffer precharge control signal PBPRCG andverification sense amplifier activation signal ATDSA. Verification ofdata in a memory cell is performed before programming (after erasureverification). If the storage data of the page buffer is the same as thedata in the memory cell, the programming operation is not performed onthis memory cell.

Command user interface 2 includes a clock generation circuit 199 thatgenerates 2-phase clock signals P1, P2 and P1_AD in accordance with theoscillation signal from this oscillator 200; an address generationcircuit 202 that sequentially updates the address value in accordancewith clock signal P1_AD under the control of the CPU not shown; and anaddress selection circuit 203 that selects either the address generatedby address generation circuit 202 or external address signal AA inaccordance with selection signal SEL to generate a programming addresssignal AO.

Address generation circuit 202 is formed of a count circuit thatperforms the counting operation sequentially starting at the initialvalue set at, for example, external address signal AA. Address selectioncircuit 203 selects the address signal from address generation circuit202 in place of external address signal AA upon the programming andverification operations to generate program address signal AO. Whenwrite-in data is written in the page buffer externally, the addressselection circuit 203 selects external address signal AA. Address signalAO from the address selection circuit 203 is supplied to the row andcolumn selection circuitry of the page buffer and the memory cell array.

An address is updated in accordance with clock signal P1_AD and thus,data write-in and read-out to the page buffer can be performed whileutilizing the clock signal as an address transition detection signal.

FIG. 26 is a diagram schematically showing the configuration of the partthat generates the voltage used in programming. Program voltagegeneration circuit 204 shown in FIG. 26 adjusts the voltage levels ofthe voltage VP transmitted onto a word line and the voltage VW suppliedto a bit line in writing (programming) under the control of CPU4 shownin FIG. 4. This voltage VP is transmitted to a word line via the rowselection circuit of the memory cell array and the voltage VW is appliedto write driver 9 and the column selection circuit of the memory cellarray. In the programming and in verification, as shown in FIG. 27, oneword line WL is selected and 16 data are successively stored. The bytedata corresponding to the lower data or the byte data corresponding tothe upper data are simultaneously stored in the region at which addressbit AE [23]=0 or 1. As shown in FIG. 27, lower byte and upper bytecorresponding to the upper word and the lower word are successivelywritten in a word (16 bits) unit for one word line.

With one word line being held in the selected state, data issuccessively written and programming and verification can be performedon external 32-word data while maintaining the voltage of word line WLat a predetermined level, and thus it becomes unnecessary to change wordlines in units of words and write-in can be performed at a high speed.

FIG. 28 is a timing chart representing an operation in verification. Inthe following, the verification operation is briefly described withreference to FIG. 28. In the verification operation, verification startinstruction signal START is set to the H level. Two clock cycles ofclock signals P1 and P2 are allocated to the verification operation ofwriting data into memory cells of 16 bits. These clock signals P1 and P2are clock signals generated by clock generation circuit 199 shown inFIG. 25 that frequency-divides two-phase clock signals PK1 and PK2generated by oscillator 200 shown in FIG. 25.

Upon start of the verification operation, first, page buffer prechargecontrol signal PBPRCG attains the H level and precharging is performedon the page buffer. Subsequently, strobe control signal STRB attains theH level, the data read-out from the page buffer is instructed, and thepage buffer data corresponding to the data to be verified is produced inaccordance with page buffer read-out control signal PBREAD. 32-bit datais read out from the page buffer and is converted to serial 16-bit dataPD [15:0] and PD [31:16] in accordance with this page buffer read-outcontrol signal PBREAD. The sensing operation is performed within thememory cell array in parallel to the data read-out from this page bufferin accordance with address transition activation signal (sense amplifieractivation signal) ATD and thereby memory cell data RD is read out. Pagebuffer read-out control signal PBREAD is activated during the firstsensing period and is inactivated in the second sensing operation.

Data is read out twice from the same memory cells of 16 bits so that2-bit data stored in each memory cell is read out. The second read-outdata RD and page buffer data PD [15:0] are latched in accordance withlatch enable signal LE (MLC_LE) and the verification result thereof isalso latched. Subsequently, coincidence or non-coincidence between thedata read out through the second sensing operation and page buffer dataPD [31:16] are subject to verification on coincidence/non-coincidence.After precharging is performed on the page buffer in accordance withpage buffer precharge instruction signal PBPRCG, data according to thisverification result are written into the corresponding memory cells.When this verification is achieved, data “1” is written in the memorycell to which programming completes, and write-in to the memory cell isprohibited afterwards.

The programming and verification operations are repeatedly performeduntil verification result indicates the accurate data writing. Withrespect to clock signals P1 and P2, two clock cycles are allocated to16-bit memory cells and programming is performed successively on 32words and verification is also performed successively on memory cells of16 words (external 32 words).

In data read-out from a memory cell, precharging time period between thefirst sensing operation and the second sensing operation is sufficientlyshort as compared with the conventional precharging period of time. Indata read-out from a memory cell, a bit line is once set at the read-outvoltage level in the first sensing operation and the voltage change ofthe bit line is small in data reading and a potential change on theverification read-out data line is extremely small, if present. Thus,bit lines and internal verification-read-out data lines can besufficiently precharged to the precharging level even if the prechargingperiod of time is shortened. The bit lines and the verification dataread-out lines are first precharged in each of the sensing periods, andthereafter the sensing operation is performed. Therefore, the senseperiod includes the precharging period and the sensing operation periodand accordingly the second sensing period of time is shorter than thefirst sensing period time, reducing the time period required for theverification.

Alternatively, the second sensing operation may be made shorter. Datasensing is performed in accordance with a binary search methodology andtherefore the potential of the read-out memory cell is one of the binaryvalues “1” and “0” on the basis of the comparison reference potential.Thus, the memory read-out potential is binary levels, unlike the casewhere the threshold voltage is different even for the same bit value andit is required to detect the different memory cell read-out potentialsas in the first sensing. Therefore, data can be precisely read out evenif the period of time for the sensing operation is reduced in the secondsensing.

FIG. 29 is a diagram schematically showing the configuration of theparallel/serial conversion part of the page buffer data included inverification circuit 52 shown in FIG. 4. In FIG. 29, the dataparallel/serial conversion part includes: a metal switch 210 thatselects either page buffer read-out control signal PBREAD or powersupply voltage Vdd; a delay circuit 212 that delays an output signal ofmetal switch 210 by a predetermined period of time; an inverter 214 thatinverts an output signal of delay circuit 212; an inverter 216 thatinverts an output signal of inverter 214; and a composite logic gate 218that selects either page buffer read-out data PD32A [15:0] or PD32A[31:16] in accordance with the output signals of inverters 214 and 216to generate page buffer data PD [15:0].

Composite logic gate circuit 218 selects lower page buffer readout dataPD32A [15:0] when the output signal of inverter 216 is at the H leveland selects upper page buffer read-out data PD32A [31:16] when theoutput signal of inverter 214 is at the H level. Accordingly, during thetime when page buffer read-out control signal PBREAD is at the H level,the first sensing operation is performed in the memory cell array sothat the lower bit data of each word is read out, and at this time, pagebuffer read-out data PD32A [15:0] is selected and page buffer data PD[15:0] is produced. When page buffer read-out control signal PBREADattains the L level and the second sensing operation is performed in thememory cell array, page buffer data PD [15:0] is generated in accordancewith page buffer read-out data PD32A [31:16].

Through the use of page buffer read-out control signal PBREAD, eitherthe upper byte data or the lower byte data of the page buffer read-outdata can be easily selected in correspondence to the memory cellread-out data from the memory cell array.

FIG. 30 is a diagram showing an example of the configuration of clockgeneration circuit 199 shown in FIG. 25. In FIG. 30, clock generationcircuit 199 includes: an oscillator 220 that performs the oscillationoperation in accordance with oscillator enable instruction signal IOSCEto generate clock signals PK1, PK2 and PK20; a latch circuit 222 thatselectively enters the latching state in accordance with clock signalPK1; a latch circuit 223 with a resetting function for selectivelyentering the latching state in accordance with clock signal PK20; aninverter 224 that inverts an output signal of latch circuit 223 fortransference to latch circuit 222; an inverter 225 that inverts theoutput signal of latch circuit 223 with the resetting function; aset/reset flip flop 226 that is set when the output signal of inverter225 is at the H level and is reset when the output signal of latchcircuit 223 with the resetting function is at the H level; an inverter227 that receives an output signal q0 of the set/reset flip flop 226; aninverter 228 that receives an output signal q1 of the set/reset flipflop 226; an inverter 229 that inverts an output signal of inverter 227to generate the clock signal P1; an inverter 2230 that inverts theoutput signal of inverter 227 for generating CPU-clock signal P1_AD; andan inverter 231 that inverts the output signal of inverter 228 togenerate the clock signal P2.

Clock signals PK1 and PK20 are 2-phase, complementary clock signals andlatch circuit 222 enters the latching state when clock signal PK1 is atthe L level and enters the through state when clock signal PK1 is at theH level. Latch circuit 223 with a resetting function enters the throughstate when clock signal PK20 is at the H level and enters the latchingstate when clock signal PK20 is at the L level. This latch circuit 223with a resetting function has its internal node NBB reset to the L levelin response to reset instruction signal RMRST.

These latch circuits 222 and 223 form a dividing circuit of clocksignals PK1 and PK20. Flip flop 226 is set or reset in accordance withthe signal of output node NAA of latch circuit 222. The flip flop 226includes NOR gate circuits having outputs and first inputs arecross-coupled and the output signal of one NOR gate circuit is suppliedto the other NOR gate circuit via a delay circuit. Accordingly,non-overlapping, 2-phase clock signals q0 and q1 are outputted from thisset/reset flip flop 226. Responsively, clock signals PK1 and PK2 arenon-overlapping, 2-phase clock signals. Clock signal P_AD is supplied toCPU and address update timing and address generation timing of addressgeneration circuit 202 shown in FIG. 25 are set in accordance with thisclock signal P_AD by the CPU.

FIG. 31 is a diagram showing an example of the configuration ofprogramming/verification control signal generation circuit 201 shown inFIG. 25. In FIG. 31, programming/verification control signal generationcircuit 201 includes: latch circuits 223 to 226 that selectively entersthe latching state in accordance with 2-phase clock signals PK1 and PK2from oscillator 220; and an inverter 237 that inverts the signal fromoutput node ND of latch circuit 236 for transmission to latch circuit233.

Latch circuits 233 and 235 enters the through state when clock signalPK1 is at the H level and enters the latching state when clock signalPK1 is at the L level. Latch circuits 234 and 236 enter the throughstate when clock signal PK2 is at the H level and enter the latchingstate when clock signal PK2 is at the L level. Latch circuits 234 and236 have a resetting function and internal output nodes NB and ND areinitialized at the L level in accordance with reset signal RMRST. Theoutput signal of latch circuit 236 is inverted by inverter 237 and istransferred to input node NDD of latch circuit 233 at the first stageand therefore a dividing circuit for bi-dividing each of clock signalsPK1 and PK2 is implemented by these latch circuits 233 to 236.

Programming/verification control signal generation circuit 201 furtherincludes: an OR gate circuit 240 that receives programming startinstruction signal MLCPBSEAN and verification operation startinstruction signal START; a composite logic gate 241 that transmit thesignal from internal output node NA of latch circuit 233 to latchcircuit 234 when the output signal of OR gate circuit 240 is at the Hlevel; an inverter 242 that inverts the signal of internal output nodeNC of latch circuit 235; a composite logic gate circuit 243 thatreceives verification operation start instruction signal START, theground voltage and the output signal of inverter 242; a metal switch 244that selects either the output signal of composite logic gate circuit243 or access timing signal MLC_ATD; and an inverter 245 that invertsthe output signal of metal switch 244 to generate memory cell arraysense amplifier activation signal ATDSA. This metal switch 244 selectsaccess timing signal MLC_ATD in the MLC configuration. An access cyclefor the memory cell array is set in accordance with this timing signalMLC_ATD. Sense amplifier activation signal ATDSA determines the sensingperiod and corresponds to timing signal ATD shown in FIG. 28.

Programming/verification control signal generation circuit 201 furtherincludes: a composite gate circuit 246 that receives the output signallatch circuit 234, the output signal of latch circuit 235 and the outputsignal of OR gate circuit 240; and an inverter 247 that inverts theoutput signal of composite gate circuit 246 to generate page buffer dataread-out control signal STRBW. Composite gate circuit 246 outputs asignal at the L level when one of the output signals of latch circuits234 and 235 is at the H level and the output signal of OR circuit 240 isat the H level.

Programming/verification control signal generation circuit 201 furtherincludes: a composite logic gate circuit 248 that generates an outputsignal in accordance with verification start instruction signal STARTand the output signal of inverter 242; and an inverter 249 that invertsthe output signal of composite logic gate circuit 248 to generate pagebuffer write-in control signal PBWRT. The composite logic gate circuit248 outputs a signal at the L level when the output of inverter 242 isat the H level and verification start instruction signal START is at theH level.

Here, the ground voltage is supplied to composite logic gate circuits241, 243, 246 and 248 because a test mode signal, which is not utilizedin a normal operation mode, is supplied.

Programming/verification control signal generation circuit 201 furtherincludes: a NAND gate circuit 250 that receives the output signal oflatch circuit 233, the output signal of OR gate circuit 240 and theoutput signal of latch circuit 234; an inverter 251 that inverts theoutput signal of NAND gate circuit 250 to generate page buffer read-outcontrol signal PBREAD; an inverter 252 that receives the output signalof latch circuit 234; a composite logic gat circuit 253 that selects andinverts either the output signal of latch circuit 233 or the outputsignal of latch circuit 235 in accordance with the output signal ofinverter 252; an AND gate circuit 254 that receives the output signal ofcomposite logic gate circuit 253 and the output signal of OR gatecircuit 240; and an inverter 255 that inverts the output signal of ANDgate circuit 254 to generate page buffer precharge control signalPBPRCG. Composite logic gate circuit 253 outputs a signal at the H levelwhen the output signal of inverter 252 is at the H level, or the outputsignal of latch circuit 234 is at the L level and the output signal oflatch circuit 233 or the output signal of latch circuit 235 is at the Hlevel.

Programming/verification control signal generation circuit 201 furtherincludes: an inverter to 256 that receives the signal from internaloutput node NA of latch circuit 233; a NAND gate circuit 257 thatreceives the signal from internal output node NB of latch circuit 236,verification start instruction signal START and the output signal ofinverter 256; an inverter 258 that receives the output signal of NANDgate circuit 257; an inverter 259 that receives the output signal ofinverter 258; a metal switch 260 that selects either the output signalof inverter 259 or power supply voltage Vdd to generate verificationsense amplifier activation signal IMLC_SA2; a NAND circuit 261 thatreceives the output signal of latch circuit 236, verification startinstruction signal START and the output signal of latch circuit 233; aninverter 262 that receives the output signal of NAND gate circuit 261and a metal switch 263 that selects either the output signal of inverter262 or the ground voltage to generate latch instruction signal MLC_LE.Metal switch 263 selects the output signal of inverter 262 in the MLCconfiguration. This latch instruction signal MLC_LE corresponds tolatching instruction signal LE in the timing chart shown in FIG. 28 andlatches the read-out data from a memory cell and the data of theverification result.

The data generated in the second sensing operation is latched inaccordance with sense amplifier activation signal IMLC_SA2. This senseamplifier activation signal IMLC_SA2 may determine the time period ofthe second sensing operation.

Programming/verification control signal generation circuit 201 furtherincludes: an inverter 264 that receives the output signal of latchcircuit 236; a composite logic gate circuit 265 that generates itsoutput signal in accordance with an output signal of inverter 256, anoutput signal of latch circuit 234 and an output signal of inverter 264;an inverter 266 that inverts the output signal of composite logic gatecircuit 265; and a NAND gate circuit 267 that receives the output signalof inverter 266 and verification operation start instruction signalSTART to generate access timing signal MLC_ATD to a memory cell.Composite logic gate circuit 265 adjusts the clock period and outputs asignal at the L level when the output signal of latch circuit 233 is atthe L level and the output signal of latch circuit 234 is at the H levelor when the output signal of latch circuit 234 is at the H level and theoutput signal of latch circuit 236 is at the L level.

Metal switch 244 selects array activation timing signal MLC_ATD fromNAND gate circuit 267 in the MLC configuration to generate timing signalATDSA and thereby, the sensing period for the array is determined byclock signals PK1 and PK2 as shown in FIG. 28.

FIG. 32 is a timing chart representing the operations of clockgeneration circuit 199 and programming/verification control signalgeneration circuit 201 shown in FIGS. 30 and 31. In the following, theoperation of the OSC circuit shown in these FIGS. 30 and 31 is describedwith reference to FIG. 32.

When it is necessary to generate a clock signal in accordance with acommand externally supplied, oscillator enable signal IOSCE is activatedso that oscillator 220 performs the oscillation operation to generate2-phase clock signals PK1 and PK2. As shown in FIG. 30, latch circuits222 and 223 carries out the signal latching/transferring operation inaccordance with clock signals PK1 and PK20 and the voltage levels oftheir internal nodes NAA and NBB change for each clock cycle of clocksignals PK1 and PK2. Accordingly, flip flop 226 is set/reset inaccordance with the signal from the internal node NAA shown in FIG. 30and, therefore, non-overlapping, 2-phase clock signals P1 and P2 havinga doubled period of clock signals PK1 and PK2 (PK20) are generated.These clock signals P1 and P2 determine the clock cycle of the internaloperation.

The timings for word line selection and the column selection in thememory cell array are determined by these clock signals P1 and P2. Inaddition, the generation timing of the control signals in theverification operation is set by these clock signals P1 and P2.

The latching state and the through state are repeated in latch circuits233 to 236 shown in FIG. 31 according to clock signals PK1 and PK2. Atthe start of the verification operation, verification operation startinstruction signal START is activated and when data is read-out from thepage buffer to be written in memory cells, page buffer sense amplifieractivation signal MLCPDSEAEN is activated.

In this programming operation or in the verification operation, theoutput signal of OR circuit 240 is at the H level and the output signalof latch circuit 233 is transmitted to latch circuit 234 by compositelogic gate circuit 241 and thereby, the voltage change sequence of theinternal nodes NB to ND, NDD and NA of these latch circuits 234, 235,236 and 233 is initialized. When the output signal of OR gate circuit240 is at the L level, internal node NB of latch circuit 234 isinitialized at the L level and therefore, the output signal of compositelogic gate circuit 241 is set at the L level independent of the voltagelevel of the internal node of latch circuit 233.

When clock signals PK1 and PK2 are generated, latch circuits 233 to 236are connected to operate as a frequency-dividing circuit and at thistime, the voltage level of internal node NB is initialized. When theoutput signal of OR gate circuit 240 is at the H level and one of theoutput signals of latch circuits 234 and 235 is at the H level, pagebuffer strobe control signal STRBW from inverter 247 is at the H level.This strobe control signal STRBW determines the activation period of thesense amplifier in the verification operation of the page buffer. Duringthe period when the voltage level of node NB is at the H level and theoutput signal of OR gate circuit 240 is at the H level and the voltagelevel of node NA is at the H level, page buffer read-out control signalPBREAD from inverter 251 is at the H level. The data of 32 bits to beverified or to be written is read out from the page buffer in accordancewith page buffer read-out control signal PBREAD.

When verification operation start instruction signal START attains the Hlevel, NAND gate circuit 267 operates as an inverter. When node NB is atthe H level and when node ND or NA is at the L level, the output signalof composite gate circuit 265 is at the L level, the output signal ofinverter 265 attains the H level and output signal MLC_ATD of NAND gatecircuit 267 attains the L level. Responsively, access activation signalATDSA is activated to be at the H level. The sense amplifier isactivated (signal MLC_ATDSA is activated) in the memory cell array, thesensing operation is performed in the memory array and 2-bit data isread out in sequence from one memory cell, in accordance with the accessactivation signal ATDSA. The activation of the sense amplifier in thepage buffer is performed, as shown in FIG. 18, in accordance with strobecontrol signal STRBW after the completion of bit line precharging.

When the voltage level of node ND is at the H level, the voltage levelof node NC is at the L level and verification start instruction signalSTART is at the H level, page buffer write-in control signal PBWRT is atthe L level. Verification start instruction signal START is set at the Hlevel during the period of the verification operation of the external 32words. Accordingly, when the strobe signal STRBW is at the L level, pagebuffer write-in control signal PBWRB is activated, writing of data intothe page buffer is performed and writing of the data of the verificationresult into the page buffer is performed.

When the voltage level of node NA is at the H level and the voltagelevel of node NB is at the H level or when the voltage level of node NCis at the H level and the voltage level of node NB is at the L level,the output signal of composite logic gate circuit 253 is at the L level,the output signal of AND gate circuit 254 is at the L level,accordingly, page buffer precharge control signal PBPRCG is at the Hlevel and bit line precharging in the page buffer is performed. Afterthe completion of precharging in the page buffer, page buffer write-incontrol signal PBWRT is activated and writing of the data of theverification result or of the page buffer data into the page buffer isperformed.

In addition, when the voltage level of node ND is at the H level and thevoltage level of node NA is at the H level, the output signal ofinverter 262 is at the H level, latch instruction signal MLC_LE isactivated and the first data read out from memory cells through thefirst sensing operation is latched.

Subsequently, during the period when the voltage level of node NA is atthe L level and the voltage level of node ND is the H level, MLC sensingactivation signal MLC_SA2 is activated and latching of the data read outthrough the second sensing operation or the second sensing operation isperformed.

Accordingly, write-in/read-out control signals to the page buffer aresequentially generated in accordance with these clock signals PK1 andPK2 and address generation/update is controlled in accordance with clocksignal P1_AD (P2) to the CPU and thereby, external data of 32 words (16word data of the internal memory cells) can be read out from the pagebuffer successively in synchronization with the clock signals, insynchronization with the data read-out from the memory cell array.

Here, when read-out of data from a memory cell array is performed, asdescribed above, the activation period of sense amplifier activationsignal MLC_ATDS is shortened in the second sensing operation.

FIG. 33 is a diagram schematically showing the configuration of the partrelated to the verification for memory cell array 10. In FIG. 33, tomemory cell array 10, there are provided a row selection circuit 270, awrite-in/verification column selection circuit 272 and a verificationsense amplifier circuit 274. The verification sense amplifier circuit274 includes 16 sense amplifiers and write-in/verification columnselection circuit 272 selects 16 pairs of bit lines simultaneously.

Row selection circuit 270 drives one word line to the selected state.The activation timings of the row selection circuit 270,write-in/verification column selection circuit 272 and verificationsense amplifier circuit 274 are determined by access activation timingsignal MLC_ATDSA. The activation timings of these circuits are set byCPU 4 shown in FIG. 4. Signal MLCATD shown in FIG. 31 or timing signalATDSA may be used as access activation timing signal MLC_ATDSA.

Two register circuits 276 and 278 are provided to verification senseamplifier circuit 274. Register circuit 276 latches the output data ofverification sense amplifier circuit 274 in accordance with latchinginstruction signal MLC_LE and register circuit 278 latches the outputdata of verification sense amplifier circuit 274 in accordance withsense amplifier activation signal MCL_SA2. Read-out data RD1 and RD2from these register circuits 276 and 278 are supplied to verificationcircuit 5 shown in FIG. 4. As described later in detail, theverification sense amplifier circuit 274 maintains the word linevoltages at the same level for the columns (bit lines) and sets thesecond sense reference current for each bit line (column) on the basisof the data read out in the first time sensing carry out the second dataread-out (sensing operation).

Here, write-in/verification column selection circuit 272 andverification sense amplifier circuit 274 are provided separately fromthe column selection circuit for data read-out. This is to prevent thecollision between the bus that transmits the external read-out data andthe bus that transmits the verification data as data reading isperformed on one bank while another bank is subject to programming.However, verification sense amplifier circuit 274 and the page buffermay be provided in common to the respective banks with the bustransmitting the verification data and the internally read out data busbeing separately provided.

In addition, the page buffer may be arranged for each respective bank ormay be arranged in common to a predetermined number of banks. In thecase where a page buffer is arranged to be shared by banks, such aconfiguration may be utilized that an external access to the page bufferis prohibited during the programming operation to a certain bank whileread-out of data from another bank is performed.

FIG. 34 is a diagram schematically showing the configuration of theverification circuit 5 shown in FIG. 4. In FIG. 34, verification circuit5 includes: a selection circuit 280 that selects 16-bit data RD1 [15:0]and RD2 [15:2] read out from memory cells in accordance with page bufferread-out control signal PBREAD; a selection circuit 282 that selectsdata PD [15:0] and PD [32:16] read out in parallel from the page bufferin accordance with page buffer read-out control signal PBREAD; acomparison circuit 284 that compares 16-bit memory cell data RD [15:0]read out from selection circuit 280 with 16-bit page buffer data PDB[15:0] outputted from selection circuit 282 bit by bit; a determinationcircuit 286 that receives comparison result signal CD [15:0] of 16 bitsfrom comparison circuit 284 to generate verification result signal PASSof one bit indicating the result of write-in pass/failure determination;and a write-in data generation circuit 288 that selects either pagebuffer data PDBD [15:0] or comparison result signal CD [15:0] inaccordance with comparison result signal CD [15:0] from comparisonresult 284 to generate write-in data ND [15:0] to the page buffer.

Selection circuits 280 and 282 select first time memory cell read-outdata RD1 [15:0] when page buffer read-out control signal PBREAD is atthe H level and the first sensing operation is performed. Data RD1[15:0] read out from this memory cell array is the upper bit data in the2-bit data stored in each memory cell and selection circuit 282 selectsupper 16-bit data PD [32:16] from the page buffer in the first time.

Comparison circuit 284 determines whether the memory cell data ranges inthe lower side threshold voltage and the upper side threshold voltage inaccordance with its internal logic to generate 16-bit signal CD [15:0]indicating the determination result.

Determination circuit 286 latches first comparison result signal CD[15:0] from comparison circuit 284 in accordance with latch instructionsignal MLC_LE and determines whether the final 32-bit data is good ordefective in accordance with comparison result signal CD [15:0] that isgenerated in the second time to generate verification result signalPASS.

Write-in data generation circuit 288 latches first comparison resultsignal CD [15:0] in accordance with page buffer read-out control signalPBREAD (or latch instruction signal MLC_LE) and selects read-out datafor the page buffer in accordance with this first determination result.In the case wherein this first comparison result signal indicatesfailure, the data of the page buffer is not changed with respect to thesecond verification result (write-in of the verification result data isprohibited). This is done for the following reasons.

Now, it is considered, as shown in FIG. 35, the operation ofover-writing data “00” into a memory cell that stores data “11”. Inprogramming operation, the threshold voltage of a memory cellsequentially increases and therefore, the storage data of the memorycell sequentially changes to the states of “11”, “10”, “01” and “00”.The data stored in the page buffer is “00” and this data serves as theexpected value data. Accordingly, in the condition where data “11” isstored, the first and second verification operations indicate both thedefective state.

In the condition where the memory cell stores data “10”, the firstverification operation indicates the defective and the secondverification operation indicates the good state. In the condition wheredata “01” is stored, the first verification operation indicates the goodstate and the second verification operation indicates the defectivestate. In the condition where data “00” is stored, the first and secondverification operations both indicate the good state.

In this verification sequence, when the second verification resultindicates the good state in the condition where data “10” is stored,data “10” is converted to data “11” to be stored in the page buffer. Inthe verification after write-in of data “01” is performed, in the casewhere the first verification operation indicates the good, the data bitfrom the page buffer at the time of the second verification is “1”,which is determined to be good and the programming operation on thismemory cell completes. Accordingly, the state is achieved where data“01” is written in place of data “00” into a write-in memory cell andtherefore, there is a possibility that a write-in error may occur.Therefore, only when the first verification is determined to be good,the second verification result is reflected in the storage data of thepage buffer. As a result, when a memory cell stores data “10”, even whenthe first verification proves defective and the second verificationproves good, the data of the page buffer is prevented from beingrewritten and thus, accurate write-in of data is achieved.

FIG. 36 is a diagram showing an example of the configuration ofcomparison circuit 284 shown in FIG. 34. In FIG. 36, comparison circuit284 includes: a register circuit 290 that takes in and outputs data RD[15:0] read out from memory cells in accordance with strobe controlsignal STRBW; an inverter 291 that receives page buffer write-ininstruction signal F2P; a NAND gate circuit 292 that receives read-outdata inversion mode instruction signal INVRTE and an output signal ofinverter 291; an inverter 293 that receives an output signal of NANDgate circuit 292; cascaded inverters 294 and 295 of two stages thatreceive page buffer check control signal PBCHK; a NAND gate circuit 296that receives data RDL [15:0] from register circuit 290 and the outputsignal of inverter 293; a NAND gate circuit 297 that receives pagebuffer read-out data PDB [15:0], the output signal of inverter 295 andthe output signal of inverter 293; an OR gate circuit that receivesmemory cell read-out data RDL [15:0] and the output signal of inverter293; a gate circuit 299 that receives page buffer read-out data PDB[15:0] as well as the output-signals of inverters 293 and 295; and aNAND gate circuit 300 that receives the output signals of these gatecircuits 296 to 299 to generate a determination result signal CD [15:0].

These gate circuits 296 to 300 each process the data of 16 bits.Register circuit 290 takes in and outputs data RD [15:0] read out frommemory cells when strobe signal STRBW is at the H level, to generatedata RDL [15:0]. When the strobe signal STRBW is at the L level, thisregister circuit 290 is in the latching state.

The types of verification operations include: over-erasure verificationmode; program verification mode for fixing the memory cell data at 1;lower side Vth checking mode for checking the threshold voltage of thelower side in the distribution of the threshold voltages of the storagedata; and in this verification circuit, page buffer write-in mode forwriting data in the page buffer, and the signals F2P, INVRDE and PBCHKas well as control signal PBLOAD not shown are set in accordance withthese modes.

FIG. 37 is a diagram showing, in a list, the logic levels of modesetting signals INVRDE, PBCHK and PBLOAD shown in FIG. 36 in theverifying modes. In the over-erasure verification mode, page buffer loadcontrol signal PBLOAD is set at the L level while read-out datainversion mode instruction signal INVRDE and page buffer check controlsignal PBCHK are both set at the L level.

In the 0 fixing verification mode of fixing memory cell data at “0”,read-out data inversion mode instruction signal INVRDE is set at the Llevel and the remaining control signals PBLOAD and PBCHK are set at theH level.

In the lower side Vth checking mode, the signal PBCHK is set at the Llevel while the remaining-control signals PBLOAD and INVRDE are set atthe L level.

In the 1 fixing verification mode of fixing the memory cell data at “1”,control signal INVRDE is set at the H level while control signals PBLOADand PBCHK are set at the L level. In the upper side Vth verificationmode, the control signals PBLOAD, INVRDE and PBCHK are set at the Hlevel.

In the mode of writing read-out data from the memory cell array orverification result data in the page buffer (PB), the signals PBLOAD andINVRDE are set at the H level while the signal PBCHK is set at the Llevel. In addition, when page buffer write-in control signal F2P is setat the H level, the data read out from memory cells is stored in thepage buffer (PB).

In the verification mode, the word line voltage is set at apredetermined read-out voltage level independent of the thresholdvoltage in the memory cell array and the comparison reference current isset at the level that corresponds to the threshold voltage of thedetection object in the sense amplifier. The state where a current flowsthrough a bit line is the erased state and corresponds to the statewhere data “1” is stored. On the other hand, when the verificationread-out voltage is applied to a word line, data “0” is read out to bemade corresponding to the programmed state when the amount of thecurrent that flows through a bit line via a memory cell is smaller thanthat of the comparison reference current supplied from the senseamplifier.

Here, in the operation of reading out the data from a memory cell in theverification, with a word line being set to a corresponding thresholdvoltage, memory cell storage data may be read depending on whether theamount of the current flowing through a bit line is greater or smallerthan that of the reference current.

In the lower side Vth checking mode, the control signal PBCHK is at theH level while the control signals INVRDE and F2P are at the L level. Inthis condition, the output signal of inverter 293 is at the L levelwhile the output signal of NAND gate circuit 296 and the output signalof NAND gate circuit 297 are both fixed at the H level. On the otherhand, OR gate circuit 298 is enabled to output memory cell data RDL[15:0]. In addition, gate circuit 299 is enabled to invert and outputpage buffer data PDB [15:0]. When one of the bits at the same positionof data RDL [15:0] and PDB [15:0] is at the L level, NAND gate circuit300 sets the corresponding verification result signal at the H level(“1”).

Accordingly, in the lower side Vth verification operation, when a memorycell is correctly programmed, the memory cell is in the state of havinga threshold voltage higher than the corresponding lower side thresholdvoltage, and a large current does not flow and data “0” is read out. Onthe other hand, gate circuit 299 inverts page buffer data PDB [15:0]. Ifthe verification operation has already been completed and correctly,data “1” is stored as the data of page buffer data PDB [15:0], thecorresponding verification result signal CD is at the H level (“1”).Accordingly, when the memory cell data is correctly programmed or whenthe data read out from the page buffer indicates the verificationcompletion, verification result signal CD [i] (i=0 to 15) is at the Hlevel, and if all 16 bits of the memory cell data are correct, all bitsof verification result signal CD [15:0] are “1”.

In the upper side Vth verification mode, control signals PBCHK andINVRDE are set at the H level. In this case, control signal F2P is atthe L level, the output signal of inverter 293 is at the H level and theoutput signal of inverter 295 is also at the H level. Thus, NAND gatecircuits 296 and 297 are enabled, the output signal of OR gate circuit298 is at the H level (for all the bits) and the output signal of gatecircuit 299 is also fixed at the H level. In this state, if either dataPDB [i] read out from the page buffer or the inverted value of memorycell data RDL [i] is “1” (H level), verification result signal CD [i] isat the H level (“1”).

In this upper side Vth verification mode, a large current flows througha memory cell correctly programmed and data “1” is read out.Accordingly, when the memory cell data is correctly programmed or whenthe verification completion is set in the page buffer, the correspondingverification result signal CD [i] is set at “1” (H level).

In the over-erasure verification mode, control signals INVRDE and PBCHKare both at the L level, the verification operation is performed inaccordance with the output signal of gate circuit 298, the output signalof logic gate circuit 299 that receives page buffer data PDB [15:0] isfixed at the H level and verification result signal CD [15:0] isgenerated in accordance with memory cell data RDL [15:0]. In theover-erasure, it is determined whether data “0” is read out when a wordline is at the L level. A current flows through a memory cell in theover-erased state so that data “1” is read out, verification resultsignal CD [i] is at the L level (“0”) indicating the over-erased stateand rewriting is performed in order to restore the over-erased state tothe erased state again.

In the upper side Vth verification, rewriting is performed whilenarrowing the write-in pulse width to a word line after applying anerasure pulse again if an error is determined.

As described later, the programming operation and the verificationoperation are performed on the 16 words of memory cells successively andprogramming and verification are performed in units of 16 words. Inother words, even if only one word is erroneously programmed, addressesare generated again for the 16 words so as to carry out programming andverification.

In the 0 fixing verification mode, the conditions of control signalsINVRDE and PBCHK are the same as in the lower side Vth checking mode andit is determined whether data “0” is read out from a memory cell.

In the 1 fixing verification mode, the control signal INVRDE is set atthe H level and the control signal PBCHK is set at the L level. In thiscase, the output signals of NAND gate circuit 297 and logic gate circuit299 are fixed at the L level and the output signal of OR gate circuit298 is fixed at the L level. Accordingly, it is determined whether data“1” exists in memory cell data RDL [15:0] in accordance with the outputsignal of NAND gate circuit 296. In this 1 fixing verification, sincedata “1” (1 bit) is written into a memory cell in accordance with thebit value of page buffer data PDB [15:0], and the corresponding pagebuffer data PDB [15:0] is set at “1” similarly and therefore, theverification operation is performed by utilizing only the memory celldata.

When control signal F2P is set at the H level, it is indicated that thememory cell data is written in the page buffer and the verificationdetermination result signal is not utilized.

FIG. 38 is a diagram showing an example of the configuration ofdetermination circuit 286 shown in FIG. 34. In FIG. 38, determinationcircuit 286 includes: NAND gate circuits 310 to 313 each receivingdifferent 4 bits of 16-bit verification determination result signal CD[15:0] from comparison circuit 284 shown in FIG. 36; a NOR gate circuit314 that receives the output signals of NAND gate circuits 310 and 311;a NOR gate circuit 315 that receives the output signals of NAND gatecircuits 312 and 313; and an AND gate circuit 316 that receives theoutput signals of NOR gate circuits 314 and 315 to generate verificationdetermination signal CD_ALL on 16 bits.

Gate circuits 310 to 316 compress 16-bit verification result signal CD[15:0] to verification determination result signal CD_ALL of 1 bit. Whenall the bits are “1” in 16-bit verification result signal CD [15:0],1-bit verification determination result signal CD_ALL is at the H level(“1”). In the case wherein at least 1 bit of the verification resultsignal of “0” exists, the corresponding output signal of NAND gatecircuits 310 to 313 attains the H level and accordingly, verificationdetermination result signal CD_ALL attains the L level.

Determination circuit 286 further includes a gate circuit 317 thatreceives control signals PBCHK, INVRDE and PBLOAD; a NOR gate circuit318 that receives output signal HF2PB of gate circuit 317 andverification determination result signal CD_ALL; a metal switch 319 thattransmits either power supply voltage Vdd or latching instruction signalMLC_LE; a register circuit 320 that takes in the output signal of NORgate circuit 318 when the output signal of metal switch 319 is at the Hlevel; a metal switch 321 that selects either the output signal of NORgate circuit 318 or the ground voltage; and a NOR gate circuit 332 thatreceives the output signal of metal switch 321 and the output signal ofregister circuit 320 to generate a final determination result signalPASS.

Gate circuit 317 sets its output signal HF2PB at the H level whencontrol signal PBCHK is at the L level and control signals INVRDE andPBLOAD are at the H level.

Metal switch 319 selects latching instruction signal MLC_LE in the MLCconfiguration, and metal switch 321 selects the output signal of NORgate circuit 318 in the MLC configuration. Register circuit 320 resetsits storage content in accordance with reset signal RMRST.

Latching instruction signal MLC_LE is kept active for a predeterminedperiod in response to the first sensing operation in data read-out fromthe memory cell array and during this period of time, register circuit320 takes in and stores the output signal of NOR gate circuit 318. Inthe verification operation, either control signal PBLOAD or INVRDE is atthe L level or control signal PBCHK is at the H level while outputsignal HF2PB of logic gate circuit 317 is at the L level and NOR gatecircuit 318 operates as an inverter to invert and output verificationdetermination result signal CD_ALL. Accordingly, when verificationdetermination result signal CD_ALL is generated in accordance with thefirst sense data, this generated verification determination resultsignal CD_ALL is stored in register circuit 320 in accordance withlatching instruction signal MLC_LE. The verification operation isperformed again on the data read out in the second sensing operation, sothat verification determination result signal CD_ALL is transmitted toNOR gate circuit 332 via metal switch 321 when verificationdetermination result signal CD_ALL is generated.

When the verification determination results of the first-time memorycell data and the second-time memory cell data are both “1” (the signalCD_ALL is inverted in NOR gate circuit 318), final determination signalPASS is set at the H level (“1”) in NOR gate circuit 332. In the casewhere final determination result signal PASS is at the H level and allthe 16-word data read out from memory cells are correctly programmed,programming for these 16 words is completed. In the case wherein even atleast one erroneously programmed word is present, the programming andverification operation is again performed in the 16 word unit (it isdetermined whether or not a programming failure exists in the 16 wordsby resetting flags in accordance with the signal PASS). Such operationis controlled by the CPU.

Here, when output signal HF2PD of logic gate circuit 317 is at the Hlevel, the output signal of NOR gate circuit 318 is fixed at the L leveland final determination result signal PASS is fixed at the H level. Inthis mode, the operation of writing the data read out from memory cellsin the page buffer (PB) is performed.

FIG. 39 is a diagram showing an example of the configuration of write-indata generation circuit 288 shown in FIG. 34. In FIG. 39, write-in datageneration circuit 288 includes: a gate circuit 340 that receivesinternal clock signal P1 and programming mode instruction signal PP aninverter 341 that receives an output signal of gate circuit 340; aregister circuit 342 that takes in external input data IOD [15:0] inaccordance with an output signal of inverter 341; a NOR gate circuit 343that receives programming mode instruction signal PP and data setupinstruction signal CDSETUP; an inverter 344 that receives an outputsignal of NOR gate circuit 343; an inverter 345 that receives an outputsignal of inverter 344; a NAND gate circuit 346 that receives the outputsignal of inverter 344 and the output signal of register circuit 342; ametal switch 347 that selects either power supply voltage Vdd or pagebuffer read-out control signal PBREAD; a register circuit 348 that takesin verification result signal CD [15:0] when the output signal of metalswitch 347 is at the H level; a delay circuit 349 that delays the outputsignal of metal switch 347; cascaded inverters 350 and 351 of two stagesthat further delay an output signal of delay circuit 349; an inverter352 that receives program sequence control signal SEC_PRG; a compositelogic gate circuit 353 that receives the output signal of registercircuit 348 and the output signals of inverters 351 and 352; a metalswitch 354 that selects either the output signal of composite logic gatecircuit 353 or the ground voltage; a metal switch 355 that selectseither the output signal of inverter 345 or the ground voltage; a NANDgate circuit 356 that receives the output signal of metal switch 354,page buffer data PD [15:0] and the output signal of metal switch 355; alogic gate circuit 357 that receives the output signal of metal switchcircuit 354, the output signal of inverter 345 and verification resultsignal CD [15:0]; an AND gate circuit 358 that receives the outputsignals of NAND gate circuits 346 and 356 as well as logic gate circuit357; and an inverter 359 that inverts the output signal of AND gatecircuit 358 to generate page buffer write-in data ND [15:0].

Composite logic gate circuit 353 equivalently includes: an OR gatecircuit that receives the output signal of inverter 351 and output dataCDF [15:0] of register circuit 348; and the output signal of this ORgate circuit and the output signal of inverter 352.

Logic gate circuit 357 is enabled when the output signal of metal switch354 is at the L level, to select and invert verification result signalCD [15:0] when the output signal of inverter 345 is at the H level.Logic gate circuit 357 outputs a signal at the H level when the outputsignal of metal switch 354 is at the H level.

Metal switch 347 selects page buffer read-out control signal PBREAD inthe MLC configuration and metal switch 354 selects the output signal ofcomposite logic gate circuit 353 in the MLC configuration. Metal switch355 selects the output signal of inverter 345 in the MLC configuration.

Data setup instruction signal CDSETUP is set at the L level when datasetup (write-in of 32-word data) is performed on the page buffer.Programming mode instruction signal PP is set at the H level in theprogramming mode including the verification operation. When programmingmode instruction signal PP is at the L level, register circuit 342 takesin and outputs external input data IOD [15:0] in accordance withinternal clock signal T1. Here, internal clock signal T1 is a clocksignal that is generated in accordance with an externally appliedcontrol signal in accessing to this nonvolatile semiconductor memorydevice and determines the input cycle of external data. In the casewhere data setup is not performed on the page buffer and the programmingmode is also not set, the output signal of inverter 344 is at the Hlevel and data from register circuit 342 is inverted and transmitted viaNAND gate circuit 346.

On the other hand, in the programming mode, register circuit 348 takesin verification result signal CD [15:0] in accordance with page bufferread-out control signal PBREAD, to generate first verification resultsignal CDF [15:0]. Register circuit 348 enters the latching state whenpage buffer read-out control signal PBREAD is at the L level.Accordingly, a signal indicating the verification result of the memorycell data read out in the first sensing operation is outputted from thisregister circuit 348.

Program sequence instruction signal SEQ PRG is set at the L level in theprogramming verification operation and is set at the H level in theprogramming operation. Accordingly, in the programming operation, theoutput signal of the inverter 352 is at the H level and the outputsignal of composite logic gate circuit 353 is at the H level when pagebuffer read-out control signal PBREAD is at the H level. On the otherhand, when page buffer read-out control signal PREAD is at the L leveland the verification result on the second read-out data from memorycells is indicated, the logic level of the output signal of thiscomposite logic gate circuit 353 is set in accordance with output dataCDF [15:0] of register circuit 348.

In the verification operation, programming mode instruction signal PPand data setup instruction signal CDSETUP are at the L level, the outputsignal of NOR gate circuit 343 is at the H level, the output signal ofinverter 344 is at the L level and the output signal of inverter 345 isat the H level. Accordingly, all the bits of the output signal of NANDgate circuit 346 are set at the H level. As for a result of theverification of the memory cell data read out in the first sensingoperation, page buffer read-out control signal PBREAD is at the H leveland the output signal of composite logic gate circuit 353 is at the Llevel and therefore, the output signal of gate circuit 357 is set inaccordance with verification result signal CD [15:0] while the outputsignal of NAND gate circuit 356 is set at the H level. Accordingly, thisfirst verification result signal CD [15:0] is selected as write-in dataND [15:0] to the page buffer. On the other hand, in the secondverification operation, when first verification result signal CDF [i] is“0” indicating a verification failure and the output signal of compositelogic gate circuit 353 is at the H level (“1”), page buffer data PD [i]is selected. On the other hand, when first verification result signalCDF [i] indicates the correct verification and is data “1”, the outputsignal of composite logic gate circuit 353 attains the L level (“0”),and verification result signal CD [i] is selected.

Accordingly, in the second sensing operation, in write-in data ND[15:0], data is set to “1”, in accordance with the verification resultsignal, for a memory cell determined to be non-defective based on theverification, and for the memory cell determined to be defective basedon the verification, data previously read out is again stored toprohibit the rewriting of corresponding storage data of the page buffer.

As a result, a problem of a programming error due to the erroneousdetermination in the verification can be prevented from occurring.

When the output signal of inverter 344 is at the H level and the outputsignal of inverter 345 is at the L level, the output signals of NANDgate circuit 356 and logic gate circuit 357 are at the H level, andwrite-in data ND [15:0] is generated in accordance with input data IOD[15:0]. Thus, external data can be written in the page buffer.

Here, this page buffer write-in data ND [15:0] may be configured to besupplied to register circuit 178 shown in FIG. 21 in the mode ofselecting externally applied input data IOD [15:0] and to be assigned towrite-in data DIN [15:0] and DIN [31:16] to the page buffer in theprogramming verification.

Although it is not clearly shown in FIG. 21, a selection circuit forselecting write-in data ND [15:0] in place of write-in data DIN [15:0]and DIN [31:16] shown in FIG. 21 is provided in this programmingverification mode. This selection circuit has its selection path set inaccordance with, for example, programming mode instruction signal PP.Alternatively, the selection circuit selects either external write-indata after the bit position conversion or write-in data from theverification circuit in accordance with data setup signal CDSETUP fortransmission to the page buffer. Write-in data ND [15:0] corresponds towrite-in data DIN [15:0] after the bit position conversion to the pagebuffer shown in FIG. 21 and first write-in data ND [15:0] and secondwrite-in data ND [15:0] are stored as the lower and upper data,respectively.

In addition, programming mode instruction signal PP and program sequencecontrol signal SEQ_PRG are activated under the control of the CPU in theprogramming mode.

FIG. 40 is a diagram showing an example of the configuration ofverification sense amplifier 360. FIG. 40 shows the configuration ofverification sense amplifier 360 for one memory cell. Since 16-bit datais read out, verification sense amplifier 360 shown in this FIG. 40 isarranged by 16 bits.

In FIG. 40, verification sense amplifier 360 includes: a P-channel MOStransistor 360 a which is connected between the power supply node andinternal node ND1 and has a gate connected to internal node ND2; aP-channel MOS transistor 360 b which is connected between the powersupply node and internal node ND2 and has a gate connected to internalnode ND2; a NAND gate circuit 360 d that receives a signal fromverification data read-out line BDE and delayed sense amplifieractivation signal MLC_ATDSA; an N-channel MOS transistor 360 c thatselectively connect node ND1 to verification data read-out line BDE inaccordance with an output signal of NAND gate circuit 360 d; andN-channel MOS transistors 360 e and 360 f which are connected in seriesbetween internal node ND2 and the ground node. A bias voltage Vrefv issupplied to the gate of MOS transistor 306 e and sense amplifieractivation signal MLC_ATDSA is applied to the gate of MOS transistor 360f.

Verification sense amplifier 360 further includes: an inverter 360 dthat inverts the voltage on verification read-out data line BDE forapplication to the gate of MOS transistor 360 c; a P-channel MOStransistor 360 g that precharges internal node ND1 to the power supplyvoltage level in accordance with sense amplifier activation signalMLC_ATDSA; and a NOR gate circuit 360 h that receives strobe controlsignal ISTRBW and the signal from internal node ND1 to generate read-outdata RD.

In the memory cell-array, there are provided a verification columnselection gate 370 selectively made conductive in accordance withverification column selection signal CSL, and a memory cell transistor372 that is connected between bit line BL and the ground node and has agate connected to word line WL. The memory cell transistor 372 has afloating gate and has the threshold voltage set in accordance with theamount of the charges stored in this floating gate.

FIG. 41 is a diagram showing the relationship between the thresholdvoltage of this memory cell 372 and the reference voltages generated foreach region of storage data. The threshold voltage region of the memorycell that stores data “11” is determined by lower side threshold voltageE1 and upper side threshold voltage E2. The threshold voltage region ofthe memory cell that stores data “10” is determined by lower sidethreshold voltage V1 and upper side threshold voltage PV1. The thresholdvoltage region for storing data “01” is determined by lower sidethreshold voltage V2 and upper side threshold voltage PV2. Only lowerside threshold voltage V3 is set for the threshold voltage region of thememory cell that stores data “00;”

In the memory cell read-out, read-out voltages R1, R2 and R3 are set asreference voltages with margins for boundary regions of the thresholdvoltage regions of data, respectively.

FIG. 42 is a timing chart representing an operation of verificationsense amplifier 360 shown in FIG. 40. In the following, the operation ofthis verification sense amplifier 360 is briefly described withreference to FIG. 42.

When sense amplifier activation signal MLC_ATDSA is at the L level, MOStransistor 360 g is in the conductive state, and internal node ND1 isprecharged to the power supply voltage level. In this state,verification read-out data line BDE is also at the L level while theoutput signal of inverter 360 d is at a high level and MOS transistor360 c is in the conductive state so that verification data read-out lineBDE is also precharged by the precharging MOS transistor 360 esimilarly. Under such condition, the voltage level of the output signalof inverter 360 d lowers when the voltage level of verification dataread-out line BDE increases, and MOS transistor 360 c has theconductance reduced to suppress the increase of the voltage level ofverification read-out data line BDE. Accordingly, MOS transistor 360 coperates in the source follower mode and maintains the voltage level ofverification read-out data line BDE at an intermediate voltage level.

In accordance with the output signal of inverter 360 d, MOS transistor360 c operates in the source follower mode to prevent the bit linevoltage from rising. As a result, channel hot electrons due to a drainhigh electrical field in the memory cell are prevented from generatingat the time of data reading out in the verification.

The sensing operation period is set by complementary strobe controlsignal ISTRBW. Here, the signals ISTRBW and STRBW are signalscomplementary to each other. A complementary signal indicates a signalthat is activated when set at the logic low level (L level). When senseamplifier activation signal MLC_ATDSA is activated, MOS transistor 360 gturns non-conductive so that precharging of internal node ND1 iscompleted and precharging of verification read-out data line BDE is alsocompleted.

In the sensing operation, in parallel, verification column selectionsignal CSL is also driven to the selected state so that bit line BLconnected to a selected memory cell and verification data read-out lineBDE are electrically coupled. The read-out voltages in the verificationare set to word line WL in accordance with the respective operationmodes. The voltage level of reference voltage Vrefv is set in accordancewith the word line voltage.

When MOS transistor 360 f is made conductive in accordance with theactivation of sense amplifier activation signal MLC_ATDSA, currents flowthrough MOS transistors 360 b, 360 e and 360 f. The mirror current ofthe current that flows through this MOS transistor 360 b flows throughMOS transistor 360 a and is supplied to verification data read-out lineBDE via MOS transistor 360 c as reference current Iref In this state,the output signal of inverter 360 d is at a high level so that MOStransistor 360 c is in the conductive state.

Cell current Icell flows in accordance with the storage data of thememory cell. In the case where this cell current Icell is greater thanreference current Iref, the voltage level of verification data read-outline BDE lowers so that the output signal of the inverter attains the Hlevel and MOS transistor 360 c is set in the deeply conductive state.Responsively, the voltage level of node ND1 lowers so that output signalRD of NOR gate circuit 360 h is set to the state (“1”) corresponding tothe voltage level (L level) of the node ND1.

In the case where reference current Iref is greater than cell currentIcell, the voltage level-of verification data read-out line BDE does notlower so that the output signal of inverter 360 d lowers below thevoltage level in the precharged stare and node ND1 is charged by thisreference current Iref and maintains the precharged state substantiallyat the H level. Accordingly, in this case, the output signal of NORcircuit 360 h attains the L level. As a result, first-time read-out ofdata of the memory cell is performed.

In the verification operation, the voltage level (Vref) of word line ischanged in accordance with the program data for the first and secondsensing operations and accordingly, the voltage level of referencevoltage Vrefv is also varied. In this case, in the verificationoperation, the word line voltage may be fixed at the read-out voltagelevel as in the normal data read out and the voltage level of referencevoltage Vrefv may be set in accordance with the data of the result ofthe first sensing operation. Either scheme can be used for the settingof the word line voltage level in this verification operation. In eitherscheme, the sensing operation is performed on the basis of thecomparison of reference current Iref with cell current Icell. FIG. 42shows the condition where verification read-out voltage of word line WLis fixed at reference voltage Vref. The voltage level of referencevoltage Vref may be changed in accordance with each sensing operation.

In the case where the word line verification voltage is changed inaccordance with the threshold voltage of the program data, referencevoltage Vrefv is also changed similarly and therefore, the relationshipbetween cell current Icell and reference current Iref at the firstsensing operation are the same as at the second sensing operation. Evenin the case where the precharging period between the first sensingoperation and the second sensing operation is short, the change in theread-out voltage of bit line BL is small and a voltage change from theprecharged voltage level is also small. Therefore, even in the casewhere the precharging period at the time of the second sensing is short,the second sensing operation can be performed by accurately prechargingbit line BL to the read-out voltage level.

In addition, as shown in FIG. 46, in the second sensing operation, evenif the voltage level of verification data read-out data line BDE differsfrom the precharged voltage level or is at a level of an insufficientprecharged voltage (case where the voltage level lowers), the voltagelevel of internal verification data read-out data line BDE furtherchanges in a direction of lowering of the voltage level and therefore,the sensing operation can be sufficiently performed even in the casewhere the activation period of sense amplifier activation signalMLC_ATDSA is short. Thus, even in the case where the precharging periodof internal node ND1 is short, the verification operation can beperformed accurately and an accurate sensing operation can be performedin the second sensing operation.

In the verification operation, the voltage level of bias voltage Vrefvis set under the control of the CPU.

As a memory cell data reading out scheme in verification, such proceduremay be employed that the word line voltage is be fixed at the voltagelevel higher than the maximum threshold voltage of the memory cell, andreference voltages Vrefv is set at the voltage levels corresponding tothe upper side threshold voltage and the lower side threshold voltage ofthe threshold voltage region of the verification object. They may beswitched between the first sensing operation and the second sensingoperation. Even in this case, the change in the voltage level ofinternal verification data read-out line BDE is small and therefore, thesensing operation- can be performed in a sufficiently precise manner.However, in this case, cell current Icell is decreased as the thresholdvoltage of the memory cell is increased and therefore, it is necessaryto set the reference voltage for the reference current Iref such thatreference current Iref is also decreased as the threshold voltage isincreased.

First Modification of Verification Sense Amplifier

FIG. 43 is a diagram schematically showing the configuration of a firstmodification of the verification sense amplifier. In the configurationof a verification sense amplifier 360 shown in this FIG. 43, averification sense precharging signal VPRG is supplied to the gate ofMOS transistor 360G for precharging internal node ND1 and a verificationsense amplifier enabling signal VSAEN is supplied to the gate of MOStransistor 360 f that activates the sensing operation.

An N-channel MOS transistor 376 selectively rendered conductive inresponse to the output signal of inverter 375 that receivescomplementary strobe timing control signal ISTRBW is provided toverification read-out data line BDE. MOS transistor 376 prechargesverification read-out data line BDE to the ground voltage level whenmade conductive. The other configuration of verification sense amplifier360 shown in this FIG. 43 is the same as the configuration of theverification sense amplifier shown in FIG. 40, and the same referencenumerals are attached to the corresponding components, and the detaileddescription thereof will not be repeated.

FIG. 44 is a timing chart representing an operation of verificationsense amplifier 360 shown in FIG. 43. In the following, the operation ofthe verification sense amplifier shown in FIG. 43 is described inreference to FIG. 44.

Complementary strobe timing control signal ISTRBW is an inverted signalof strobe control signal STRBW and determines the sensing operationperiod. When the sense amplifier operates, complementary strobe timingcontrol signal ISTRBW makes transition from the H level to the L level.When the precharging operation by MOS transistor 376 on verificationread-out data line BDE is completed, verification data read-out dataline BDE attains the floating state at the ground voltage level.

When complementary strobe timing signal ISTRBW attains the L level,precharging instruction signal IBPRG is set at the L level for apredetermined period and internal node ND1 is precharged by MOStransistor 360 g. In the precharging operation, MOS transistor 360 c isin the conductive state in accordance with the output signal of inverter360 d and operates in the source follower mode and thereforeverification read-out data line BDE is also precharged to anintermediate voltage level.

When this precharging operation is completed, verification senseamplifier activation signal VSAEN is activated (at the H level), so thatreference current Iref determined by reference voltage Vrefv flows ontoverification read-out data line BDE. At this time, as in the timingshown in FIG. 42, in the activation of the sense amplifier, columnselection signal CSL rises to the H level and cell current Icell flowsinto bit line BL. If cell current Icell that is driven by the memorycell 372 is greater than reference current Iref, the voltage level ofverification read-out data line BDE lowers and the voltage level ofinternal node ND1 having a small load capacitance drops rapidly.Read-out data RD from NOR gate circuit 360 h attains the H level inaccordance with the drop of the voltage level of internal node ND1 andthus data “1” is read out.

Subsequently, when the sense amplifier activation signal VSAEN isdeactivated, precharging instruction signal IVPRG attains the L level atthe same time, and the precharging of internal node ND1 is performed. Atthis time, the activated period of precharging instruction signal IVPRGis shorter than the activated period in the first time and therefore thevoltage levels of verification read-out data line BDE and internal nodeND1 are not completely recovered to the power supply voltage level, butare maintained at an intermediate voltage level. When the prechargingoperation is completed, verification sense amplifier activation signalVSAEN is again activated and a corresponding reference current Iref issupplied. When reference current Iref is larger than cell current Icell,the voltage level of internal node ND1 rises so that data “0” is readout as data RD.

The voltage level of verification read-out data line BDE in theprecharged state is an intermediate voltage level and the output signalof inverter 360 d is at the H level or at an intermediate voltage levelso that MOS transistor 360 c maintains the conductive state.

When this sensing operation is completed, complementary strobe timingcontrol signal ISTRBW attains H level and verification sense amplifieractivation signal VSAEN is deactivated so that precharging ofverification read-out data line BDE to the ground voltage level is againperformed. Precharging instruction signal IVPRG is at the H level andinternal node ND1 is precharged to the ground voltage level via MOStransistor 360 c (the output signal of inverter 360 d is at the Hlevel).

Even in the case where the second precharging period is shorter than thefirst precharging period, the change in the voltage level ofverification read-out data line BDE is still small due to the cellcurrent in the memory cell selection, and therefore verificationread-out data line BDE is sufficiently precharged to a level in thevicinity of a predetermined voltage level even when this secondprecharging period is short.

FIG. 45 is a diagram showing an example of the configuration of the partthat generates the control signals to the verification sense amplifiershown in FIG. 43. In FIG. 45, the verification sense amplifier controlsignal generation circuit includes: an inverter 390 that receives strobetiming control signal STRBW; a delay circuit 391 that delays strobetiming control signal STRBW by a predetermined period of time; a delaycircuit 392 that further delays the output signal of delay circuit 391;a delay circuit 393 that delays the output signal of inverter 390; an ORcircuit that receives output signal ISTRBW of inverter 390 and theoutput signal of delay circuit 391; an OR circuit 395 that receives theoutput signals of delay circuits 392 and 393; an AND circuit 396 thatreceives the output signals of OR circuits 394 and 395 to generateprecharge control signal IVPRG; and an AND circuit 397 that receivesstrobe timing control signal STRBW and the output signal of AND circuit396 to generate verification sense enable signal VSAEN.

The first precharging period is determined by the delay time set bydelay circuit 391 and the second precharging period is determined bydelay circuits 392 and 393. The first sensing period is determined bydelay circuit 392 and the second sensing period is determined by theoutput signal of delay circuit 392 and strobe timing control signalSTRBW.

In the sensing operation, strobe timing control signal STRBW is at the Hlevel, AND circuit 397 operates as a buffer circuit, and generatesverification sense enable signal VSAEN in accordance with precharginginstruction signal IVPRG. As a result, the verification sensingoperation can be achieved in which the second precharging period and thesecond sensing period are shorter than the first precharging period andthe first sensing period, respectively.

Second Modification of Verification Sense Amplifier

FIG. 46 is a diagram showing the configuration of a second modificationof the verification sense amplifier. In FIG. 46, the verification senseamplifier includes: a P-channel MOS transistor 400 which is connectedbetween the power supply node and node ND10 and has a gate connected tonode ND11; a P-channel MOS transistor 401 which is connected between thepower supply node and node ND 11 and has a gate connected to nod eND11;N-channel MOS transistors 402, 403 and 404 which are coupled to nodeND11 and have the respective gates receiving reference voltages VREF0,VREF1 and VREF2; and N-channel MOS transistor 405, 406 and 407 which arerespectively connected between MOS transistors 402 to 404 and the groundnode. Activation signals ISAES, SAE_L and SAE_U are supplied to thegates of N-channel MOS transistor 405, 406 and 407, respectively.

The verification sense amplifier further includes: a P-channel MOStransistor 410 which receives, at a gate, sense activation signalTXLATDE and precharges node ND10 to the level of power supply voltageVdd when made conductive; a NOR gate circuit 412 that receives theoutput signal of inverter 411 and the signal from node ND10; an inverter413 that receives the output signal of NOR gate circuit 412; an inverter414 that inverts an output signal of inverter 413 to generate internalread-out data RD; a transfer gate circuit 415 that is renderedconductive when complementary second sense enable signal ISAES isinactive (H level), to transmit the output signal of inverter 413; aninverter latch circuit 416 for latching an output signal of inverter 413transmitted via transfer gate circuit 415; a NOR gate circuit 417 thatreceives the latch signal of inverter latch circuit 416 andcomplementary second sense enable signal ISAES to activate upper senseenable signal SAE_U; and a NOR gate circuit 418 that generates lowersense enable signal SAE_L in accordance with complementary second senseenable signal ISAES and the latch data of inverter latch circuit 416.

Inverter latch circuit 416 includes: an inverter 416 a that receives theoutput signal of inverter 413 via transfer gate circuit 415; and aninverter 416 b that inverts the output signal of this inverter 416 a fortransmission to the input of inverter 416 a. The output signal ofinverter 416 a is supplied to NOR gate circuit 417 and the output signalof inverter 416 b is supplied to NOR gate circuit 418.

The verification sense amplifier further includes: an N-channel MOStransistor 408 which is connected between node ND10 and verificationdata transmission line BD; and an inverter 409 that inverts andamplifies the signal from verification data transmission line BD fortransmission to the gate of MOS transistor 408. Inverter 409 lowers thegate voltage level of MOS transistor 408 when the voltage level ofinternal data line BD rises, to prevent the voltage level of thisverification data transmission line BD from rising to the level of powersupply voltage Vdd. As a result, the bit line voltage is prevented fromrising when a read-out current is supplied to the bit line, to preventchannel hot electrons from being generated and injected into floatinggate of a memory cell transistor (soft program) in the verificationread-out.

Sense amplifier activation signal TXLATDE is activated at the time ofdata read-out of a memory cell in the verification and in when the dataaccessing and is a signal equivalent-to the sense amplifier activationsignal ATDSA in the verification.

The operation of the verification sense amplifier shown in this FIG. 46in the data read-out is described with reference to FIGS. 47 and 48.Here, as shown in FIG. 47, a case is considered where storage data “10”of a memory cell is read out. In a normal data read-out, a voltagehigher than any of the distributed threshold voltages of the memorycells is applied to a word line of memory cells so that all the memorycells are set to the conductive state. The amount of the drive currentdiffers for different threshold voltage of a memory cell. The higher thethreshold voltage is, the smaller is the amount of the drive current ofa memory cell.

In the verification sense amplifier shown in FIG. 46, node ND10 is firstprecharged to the power supply voltage level by MOS transistor 410before the start of the sensing operation. Verification read-out datatransmission line BD is precharged to a predetermined voltage level (setby the voltage limiting function of MOS transistor 408). When thisprecharging operation is completed, second sense enable signal ISAES isat the H level and therefore upper sense enable signal SAE_U and lowersense enable signal SAE_L from NOR gate circuits 416 and 418 are both atthe L level. Accordingly, MOS transistor 405 is made conductive togenerate reference current Iref in accordance with reference voltageVREF0. This reference voltage VREF0 is set at the voltage levelintermediate the threshold voltages. The threshold voltage of the memorycell is lower than this reference voltage VREF0 and therefore cellcurrent Icell is larger than reference current Iref and the voltagelevel of verification read-out data transmission line BD is lowered andresponsively, the voltage level of node ND10 also lowers. Complementarysecond sense enable signal ISAES is at the H level and thereforetransfer gate circuit 415 is in the conductive state and the signal atthe L level from inverter 413 is latched by inverter latch circuit 416.

When the first sensing operation is completed, complementary secondsense enable signal ISAES falls to the L level, and responsively thelower sense enable signal SAE_L from NOR gate circuit 418 rises to the Hlevel. At this time, even if the first sensing operation and the secondprecharging operation are performed, transfer gate circuit 415 is in thenon-conductive state, and therefore the latch data of this latch circuit416 is not adversely affected. However, this complementary second senseenable signal ISAES may be driven to the L level in synchronization withthe timing of the start of the second precharging operation so as toswitch the reference voltages (here, it is necessary to adjust thetiming such that the latch data of latch circuit 416 is not adverselyaffected by the second precharging operation).

MOS transistor 406 is made conductive by the lower sense enable signalSAE_L, to generate reference current Iref in accordance with referencevoltage VREF1. This reference current Iref corresponds to the thresholdvoltage level that is lower than the threshold voltage of the memorycell and reference current Iref becomes greater than cell current Icell,so that node ND10 rises to the precharged voltage level while read-outdata RD from inverter 414 attains the L level or “0”. Accordingly, data“10” can be read out precisely with the word line voltage fixed.

This data read-out operation is utilized to perform the verificationoperation. In this verification operation, the level of the referencevoltage is changed. In this case, when the word line voltage is set at aread-out voltage level the same as in a normal data reading, dataread-out can be performed in accordance with the same sequence whileperforming the similar verification operation.

Modification of Verification Operation Sequence

FIG. 49 is a diagram illustrating the data read-out operation in theverification operation. FIG. 49 also shows the verification referencevoltages in the case where the programmed state of data “10” isverified. In this case, the respective lower side threshold voltagelevels of the threshold voltage regions of data “01”, “10” and “00” areutilized as reference voltages REF0, REF1 and REF2. First, a voltagethat corresponds to the lower side threshold voltage of data “01” isselected as reference voltage REF0 and corresponding reference currentIref is generated. In this case, the word line verification voltage isat the level of the upper side threshold voltage of data “10” or at thevoltage level having a margin relative to the same. In this firstsensing operation, reference basis voltage REF0 generates referencecurrent Iref that corresponds to the state of a higher threshold voltagethan the threshold voltage of the memory cell that stores data “10”.Accordingly, reference current Iref is an extremely small current. Onthe other hand, a memory cell is made conductive in accordance with theword line verification voltage and cell current Icell is larger thanreference current Iref and therefore data “1” is read out in the firstsensing operation.

Subsequently, a voltage level for supplying a cell current thatcorresponds to the lower side threshold voltage of data “10” is selectedas reference voltage REF1 following the first sensing operation. Thisreference voltage REF1 generates reference current Iref larger than cellcurrent Icell of the memory cell storing data “10” and therefore data“0” is read out in the second verification operation. In a memory cellthat stores “11”, a current that is larger than this reference currentIref is driven at the time of this second sensing operation andtherefore data “1” is read out.

Upon the verification of data “01”, the word line verification voltageis set at a voltage level between the threshold voltages of data “01”and data “00”. As the reference voltage, such a reference voltage isused that a current driven by a threshold voltage the same as thevoltage level between data “10” and data “01” is produced as thereference current. As for data “01”, reference current Iref is largerthan cell current Icell and therefore data “0” is read out in firstsensing operation. As for memory cells that store data “11” and data“10,” cell current Icell is larger than reference current Iref andtherefore data “1” is read out. Accordingly, when data “0” is read outin the first sensing operation, then reference voltage REF2, forexample, which is the same in voltage level as the word line voltage, isselected in the second sensing. In this case, in memory cells that storedata “01”, cell current Icell is larger than reference current Iref andtherefore data “1” is outputted. In memory cells that store data “00”,cell current Icell is smaller than reference current Iref and therefore,data “0” is read out. In this case, data “1” is read out also from thememory cells that store data “10.” However, in the programmingoperation, the programming operation is performed such that thethreshold voltage is sequentially increased and the verificationoperation is completed for the memory cells that store data “10”, andtherefore data bit “1” indicating the completion of verification isstored in the page buffer, raising no particular problems. Data of thememory cells to be verified need only to be precisely read out.

As a result, even in the case where the word line verification voltageis fixed in accordance with the verification data, data can be preciselyread out to perform the accurate verification.

Here, if the word line voltage is changed in accordance with thereference voltage or is set at the word line read-out voltage level setin data accessing, these verification sense amplifiers can be used toprecisely read out the memory cell data in accordance with thesequential sensing scheme even in the general verification operation inwhich no re-writing of data in the page buffer is performed.

The verification sense amplifier shown in FIG. 46 has been described asa sense amplifier for verification. However, it can be utilized as asense amplifier for data read-out in external the data read-out. Inaddition, a sense amplifier for data read-out and a sense amplifier forverification may be formed into a common amplifier.

Configuration of Reference Voltage Generation Part

FIG. 50 is a diagram schematically showing the configuration of the partthat generates reference voltages VREF0 to VREF2 (VREF0-2). In FIG. 50,this nonvolatile semiconductor memory device includes a memory cellarray 500 and a memory cell selection circuit 502 for selecting a memorycell of memory cell array 500. In memory cell array 500, memory cells MCare formed of floating gate-type field effect transistors and memorycells MC are arranged in rows and columns. Word lines are arrangedcorresponding to respective rows and bit lines are arrangedcorresponding to the respective columns. In FIG. 50, one memory cell MCin memory cell array 500 and word line WL that is connected to this cellare representatively shown.

Memory cell selection circuit 502 includes a memory cell row selectioncircuit and a memory cell column selection circuit. In memory cellcolumn selection circuit, a data read-out column selection circuit for anormal data accessing and a verification column selection circuit may beseparately provided, or a common column selection circuit may be usedfor verification and for normal data read-out. In addition, a write-incolumn selection circuit for transferring the output signal of the datawriting write driver to the selected bit line and a column selectioncircuit for data read-out may be provided separately. In programming,verification and programming are performed utilizing the verificationcolumn selection circuit, and data read-out may be performed byconnecting a selected bit line to a sense amplifier via an internalread-out data line by the use of the data read-out column selectioncircuit. Accordingly, the configuration of the column selection circuitis appropriately determined in accordance with the array configuration.

A sense amplifier circuit 504 is provided to this memory cell array 500.This sense amplifier circuit 504 may include a sense amplifier forverification and a sense amplifier for data read-out separately. In thebank configuration, a sense amplifier for external read-out that readsout the data of the memory cell array may be provided in common to allthe banks while a sense amplifier for verification may be arranged foreach of the banks of the memory cell array. Accordingly, theconfiguration of this sense amplifier circuit 504 is also appropriatelydetermined in accordance with the configuration of memory cell array500.

A reference voltage generation array 510 and a reference voltage settingcircuit 512 for setting the voltage levels of reference voltages VREF0to VREF2 generated by this reference voltage generation array 510 areprovided to this memory cell array 500. Reference voltage generationcircuit 510 is formed by arranging memory cells of the sameconfiguration as memory cells MC included in memory cell array 500. Areference voltage is generated on the basis of a current that flowsthrough a selected memory cell in reference voltage generation array510. Reference voltage generation array 510 and memory cell array 500are the same in memory cell structure, and the variation of thecharacteristics of the memory cells in memory cell array 500 can bereflected in the reference voltage generated by reference voltagegeneration array 510, and thus the reference voltage can be preciselygenerated. The reference voltage generated by this reference voltagegeneration array 510 is utilized as the reference voltage senseamplifier circuit 504 and in addition, is utilized as the verificationread-out voltage in the case where a selected word line is set at theverification read-out voltage corresponding to the threshold voltagelevel in the verification.

Reference voltage setting circuit 512 sets the voltage levels ofreference voltages VREF0 to VREF2 generated by the reference voltagegeneration array 510 in accordance with the operation mode under thecontrol of the CPU not shown (see FIG. 4).

FIG. 51 is a diagram schematically showing an example of theconfiguration of reference voltage generation array 510 shown in FIG.50. In FIG. 51, reference voltage generation array 510 includesreference voltage array blocks RFBK0 to RFBK2 provided corresponding tothe respective reference voltages VREF0 to VREF2. These referencevoltage array blocks RFBK0 to RFBK2 have the same configuration andtherefore, FIG. 51 representatively shows the configuration of referencevoltage array block RFBK0.

Reference voltage array block RFBK0 (RFBK1 and RFBK2) includes aplurality of memory blocks MBK0 to MBKn. 16 to 32 memory blocks areprovided as these memory blocks MBK0 to MBKn. Memory blocks MBK0 to MBKnhave the same configuration and therefore, FIG. 51 representativelyshows the configuration of one memory block MBK0. Main bit line MBL isprovided to these memory block MBK0 (MBK1 to MBKn). Four sub-bit linesSBL0 to SBL3 are provided to the main bit line MBL in memory block MBK0and reference word line RWL is provided in the direction crossing themain bit line MBL and sub-bit lines SBL0 to SBL3. Sub-bit lines SBL0 toSBL3 are -coupled to main bit line MBL via selection gates CG0 to CG3,respectively. These selection gates CG0 to CG3 are selectively madeconductive in accordance with sub-bit-line selection signals SG0 to SG3.Selection gates CG0 to CG3 for selecting the sub-bit lines are arrangedon opposite sides of the sub-bit lines and the pitch of selection gatesCG0 to CG3 can be mitigated.

Reference cells RC0 to RC3 of the floating gate-type the same inconfiguration as memory cells MC are arranged corresponding to thecrossings of reference word line RWL and sub-bit lines SBL0 to SBL3.These reference cells RC0 to RC3 have threshold voltages made differentfrom each other.

A column selection gate YG rendered conductive in response to columnselection signal Y, a mat selection transistor BG that receives matselection signal CAU indicating upper/lower array mat selection, a biastransistor BT that receives bias voltage BIAS for limiting a rise involtage level of the main bit line, and a P-channel MOS transistor(insulating gate-type field effect transistor) P type which is connectedbetween the power supply node and bias transistor B and having the gateand the drain interconnected, are connected in series to main bit lineMBL of each of memory blocks MBK0 to MBKn.

The configuration in which column selection gate YG, mat selection gateBG and bias transistor BT are connected is the same as the configurationprovided to main bit line MBL in memory cell array 500, and the main bitline is connected to the internal data read-out line (or verificationdata line) via this bias transistor BT in memory cell array 500.

Reference voltage array block RFBK (RFBK1 and RFBK2) further includes: adummy gate transistor YGR that is made conductive by receiving the powersupply voltage at its gate; a reference voltage generation transistorBGR for current/voltage conversion having the gate and the drainconnected together, a bias transistor BTR that receives bias voltageBIAS at its gate, and a current source transistor PTR having a gateconnected to all of the gates of MOS transistors PT (current sourcetransistors) of each respective memory block. Transistors YGR, BGR andBTR, YG, BG and BT are formed of N-channel MOS transistors while currentsupply transistor PTR is formed of a P-channel MOS transistor. MOStransistors YGR, BGR, BTR and PTR are connected in series.

The size ratio (channel width to channel length ratio) of MOS transistor(current source transistor) PT to MOS transistor PTR is adjusted to anappropriate value.

FIG. 51 shows that these reference array blocks RFBK0 to RFBK2 arearranged in separate blocks. However, these reference array blocksRFBK0, RFBK1 and RFBK2 may be arranged so as to share reference wordline RWL and to include different groups of main bit lines.

FIG. 52 is a diagram showing an example of the configuration ofreference cells RC0 to RC3 shown in FIG. 51. As shown in this FIG. 52,reference cells RC0 to RC3 are formed of floating gate-type transistorshaving the same configuration as memory cells MC and have the thresholdvoltage Vth adjusted in accordance with the level of the referencevoltage to be generated. A threshold voltage according to the storagedata of a memory cell may be used as this threshold voltage Vth.

FIG. 53 is a diagram schematically showing the size ratio of currentsource transistor PT to current source transistor PTR shown in FIG. 51.As shown in FIG. 53, the size ratio of current source transistor PT,which is provided to each of memory blocks MBK0 to MBKn, to currentsource transistor PTR for reference voltage generation is set at1:1/(n+1). Current source transistors PT and PTR form a current mirrorcircuit with current source transistor PT being a master transistor, andtherefore a current which is 1/(n+1) times larger than the sum of thecurrents flowing through current source transistors PT in memory blocksMBK0 to MBKn flows via current source transistor PTR. Accordingly, inthe case where current source transistors PT corresponding to memoryblocks MBK0 to MBKn generate currents I0 to In, respectively, current Irgenerated by current source transistor PTR for reference voltagegeneration assumes (I0+ . . . +In)/(n+1). The variation of the thresholdvoltages of reference cells RC (RC0 to RC3) in memory blocks MBK0 toMBKn can be averaged so that reference current Ir at a desired stablelevel can be generated to generate reference voltage VREF.

Selection signals SG0 to SG3 are set in accordance with the operationmode and a reference cell generating a reference current correspondingto the operation mode is selected in reference cells RC0 to RC3, andaccordingly, reference current Ir has the current flow level set at thecurrent level according to the operation mode, so that the voltage levelof reference voltage VREF can be set. The reference voltages VREF0-2 canbe utilized as reference voltages for the sense amplifiers shown in FIG.40 et. seq., and in addition, can be utilized as the reference voltagestransmitted onto a word line in the case where the word line is set atthe verification voltage according to the threshold voltage.

Reference currents in the respective operation modes, such as in thedata read-out mode, in programming, erasure and verification, can begenerated in the same circuit configuration, and therefore control issimplified and the circuit occupation area can be reduced.

Here, the configuration of the reference voltage generation part shownin FIG. 51 can be utilized as a circuit that generates a referencevoltage for the cell array of the SLC configuration, in addition to theMLC configuration.

First Modification of Reference Voltage Generation Part

FIG. 54 is a diagram schematically showing the configuration of a firstmodification example of the reference voltage generation part. In FIG.54, reference word lines RWL2, RWL0 and RWL1 are provided correspondingto reference voltages REF2, REF0 and REF1, respectively. Drive voltagesDIVW0 to DIVW2 are supplied to these reference word lines RWL0 to RWL2from reference word line drive voltage generation circuit 520. Thisreference word line drive voltage generation circuit 520 includes: anactivation transistor 520 a formed of a P-channel MOS transistor andcoupled to the node supplying a word line read-out voltage VBOOST, andmade selectively conductive in accordance with activation signal /EN;and resistance elements RZ1 to RZ4 connected in series betweenactivation transistor 520 a and the ground node.

Divided voltages DIVW2, DIVW0 and DIVW1 are generated from therespective connection nodes of these resistance elements RZ1 to RZ4 andare supplied to reference word lines RWL2, RWL0 and RWL1, respectively,as the drive voltages.

Word line read-out voltage VBOOST is generated in accordance with theoperation mode from an internal voltage generation circuit not shown, isa voltage that is transmitted onto a selected word line in data read-outaccess of memory cell array 500 and is set at a voltage level higherthan the maximum threshold voltage of the multi-level data. The wordline may be set at the read-out voltage VBOOST level in the verificationoperation.

Reference cells RCA, RCB and RCC are connected to reference word linesRWL2, RWL0 and RWL1, respectively, and are connected to sub-bit linesSBLA, SBLB and SBLC, respectively. These sub-bit lines SBLA to SBLC arecoupled to main bit lines MBLA to MBLC via selection gates CGA to CGC,respectively. These selection gates CGA to CGC enter the conductivestate at the same time in accordance with selection signal SGEN.

Main bit lines MBLA to MBLC are coupled to current mirror-type circuits530 a to 530 c. Current mirror-type circuits 530 a to 530 c convertmirror currents of the currents flowing through corresponding main bitlines MBLA to MBLC, to voltages to generate reference voltages VREF2,VREF0 and VREF1, respectively.

Reference cells RCA to RCC are each in the erased state and have thesame threshold voltage. Accordingly, drive currents are changed inaccordance with divided voltages DIVW0 to DIVW2 transmitted onto thecorresponding word lines. Corresponding reference voltages VREF0 toVREF2 can be generated in accordance with drive voltages DIVW0 to DIVW2generated from reference word line drive voltage generation circuit 520.

Here, main bit lines MBLA to MBLC each may be an assembly of main bitlines MBL of reference array blocks RFBK0 to RFBK2, respectively, shownin FIG. 51 (in this case, the reference voltage is generated on thebasis of the averaged current), or may be a single main bit line (noaveraged current is generated).

In the case where reference array blocks RFBK0 to RFBK2 shown in FIG. 51are utilized, current mirror-type circuits 530 a to -530 c eachcorrespond to the combination of transistors YGR, BGR, BTR and PTR.Required reference voltages VREF0 to VREF2 can be generated by dividingread-out voltage VBOOST transmitted onto a word line.

Here, activation signal /EN is activated in the operation mode thatrequires a reference voltage in the data access or verification. Areference voltage at another voltage level generated in programverification and in erasure verification is also generated from anotherreference cell. A plurality of groups of selection gates CGA to CGC areprovided to select a group of the selection gates for a requiredreference voltage in accordance with the selection signal.

In addition, a circuit the same in configuration as reference word linedrive voltage generation circuit 520 but different in dividing factor ofthe resistors is provided in parallel to generate reference word linedrive voltages DIVW0 to DIVW2, and reference voltages required for theverification voltage in programming and in erasure can be generated.

In addition, reference memory cells having different threshold voltagesare connected to the same reference word line RWL, and a plurality ofreference voltages may be generated from one selected reference wordline. A reference word line is selected in accordance with the operationmode and thus a plurality of reference voltages according to theoperation mode are generated. In this case, in the configuration shownin FIG. 51, divided voltage DIVW may be supplied to reference word lineRWL as the drive voltage.

FIG. 55 is a diagram showing an example of the configuration of currentmirror-type circuits 530 a to 530 c shown in FIG. 54. These currentmirror-type circuits 530 a to 530 c have the same configuration, andtherefore FIG. 55 representatively shows these current mirror-typecircuits 530 a to 530 c as a current mirror-type circuit 530.

Current mirror-type circuit 530 includes: a P-channel MOS transistor 535which is connected between the power supply node and node ND20 and has agate connected to node ND20; an N-channel MOS transistor 536 which isconnected between node ND20 and node ND22; an inverter 537 that invertsthe voltage level of node ND22 for transmission onto the gate of MOStransistor 536; an N-channel MOS transistor 538 which is connectedbetween node ND22 and main bit line MBL (MBLA to MBLC) and has a gateconnected to the power supply node and serves as a dummy gate; aP-channel MOS transistor 539 which is connected between the power supplynode and node ND24 and has a gate connected to node ND20; and N-channelMOS transistors 540 and 541 which are connected in series between nodeN24 and the ground node.

MOS transistor 540 has a gate connected to node ND24, and functions as acurrent/voltage conversion element to generate reference voltages VREF(VREF0 to VREF2). MOS transistor 541 receives activation signal EN atits gate and activates current mirror-type circuits 530 a to 530 c at atiming at which this reference voltage VREF is generated.

In current mirror-type circuit 530, MOS transistors 535 and 539 form acurrent mirror circuit with MOS transistor 535 being the master, and MOStransistor 539 generates a mirror current of the current flowing throughmain bit line MBL. MOS transistor 540 converts the mirror currentsupplied from this MOS transistor 539 to a voltage to generate referencevoltage VREF. Accordingly, reference voltages corresponding to thecurrents flowing through corresponding reference cells RCA to RCC frommain bit line MBL are precisely generated. In particular, this currentmirror-type circuit 530 has the same configuration as the senseamplifier, as shown in FIGS. 43 to 46, and can generate referencevoltage VREF while precisely reflecting (compensating for) the amount offluctuation in the resistance components of the reference current in thesense amplifier.

Here, in the configuration shown in FIG. 55, the averaged currentgenerated by current source transistor PTR may also be supplied to MOStransistor 538, as shown in FIG. 51. Current source transistor PTR maybe connected to MOS transistor 538 or may be connected to node ND22. Thereference voltage VREF can be generated while averaging thecharacteristics of the reference cells.

Modification of Reference Cell

FIG. 56 is a diagram showing a modification of reference cell RC. In theconfiguration of reference cell RC shown in this FIG. 56, a control gateCG and a floating gate FG are connected together and are supplied with adivided voltage (drive voltage) DIVW. Control gate CG and floating gateFG of the transistor having the same structure as the memory celltransistor are connected to each other and thus, the memory celltransistor of the stacked gate can be operated as a single gate MOStransistor and a reference current can be generated in accordance withdivided voltage DIVW while reflecting the characteristics of the memorycell transistors.

Even if the threshold voltage of reference cell RC is the same for allthe reference cells, the threshold voltage is equivalently adjusted bydivided voltage DIVW so that the drive current can be adjusted.Moreover, the threshold voltage may be adjusted in accordance with therequired reference voltage. In this case, the drive current of thereference cell is determined in accordance with divided voltage DIVW andthe threshold voltage of the reference cell, so that a wide variety ofkinds of reference voltages can be generated.

Reference cell RC shown in FIG. 56 may be arranged in reference voltagegeneration array block RFBK0-2 shown in FIG. 51. In addition, the sizeof reference cell RC may be changed in accordance with the referencevoltage to be generated.

Second Modification of Reference Cell

FIG. 57 is a diagram showing the configuration of a second modificationof reference cell RC. In FIG. 57, reference cell RC is formed of asingle gate MOS transistor 550. This MOS transistor 550 does not have afloating gate, and has only a control gate. The size of MOS transistor550, or the ratio W/L of the channel width to the channel length is setin accordance with reference voltage VREF.

Divided voltage DIVW of word line read-out voltage VBOOST or anappropriate reference word line selection voltage is supplied toreference word line RWL and thereby, drive current differs in accordancewith reference voltage VREF, so that the corresponding reference voltagecan be generated.

Accordingly, when MOS transistor 550 shown in FIG. 57 are arranged asreference cells RC0-RC as shown in FIG. 51 with sizes (W/L) madedifferent, reference voltages required in the MLC configuration and inthe SLC configuration can be generated even in the case wherein thethreshold voltages of the reference cells are all the same.

In the configuration of reference cell RC shown in this FIG. 57, MOStransistor 550 that forms reference cell RC is fabricated in the samefabrication process of peripheral transistors such as the columnselection gates of the memory cell array and thus, MOS transistorshaving sizes according to the respective reference voltages can beformed without increasing the number of manufacturing steps.

Configuration of Read-out/Output Circuit

FIG. 58 is a diagram schematically showing the configuration ofread-out/output circuit 11 shown in FIG. 4. In FIG. 58, the nonvolatilesemiconductor memory device includes: a read-out address generationcircuit 600 that is activated in data read-out to generate internalread-out address bits AE [23:0] from external address bits AA [23:0]; amemory cell row selection circuit 602 that selects a memory cell row ofmemory cell array 10 in accordance with internal address bits AE [23:5]from read-out address generation circuit 600; a read-out columnselection control circuit 606 that controls the column selection of thememory cell array and the data read-out operation in accordance withinternal read-out address bits AE [4:3] from read-out address generationcircuit 600; a data read-out circuit 604 that selects a memory cellcolumn from the selected memory cell row of memory cell array 10 to readout data under the control of the above read-out column selectioncontrol circuit 606; a data transfer output circuit 608 thatsequentially transfers the data read out from data read-out circuit 604to generate 16-bit data D [15:0]; and a transfer/output bit selectioncontrol circuit 610 that controls the data transfer bit under the datatransfer operation of data transfer output circuit 608 in accordancewith internal read-out address bits AE [23] and AE [1:0] from read-outaddress generation circuit 600.

Data read-out circuit 604 is coupled to data transfer output circuit 608via the internal output data bus of 128 bits. This data transfer outputcircuit 608 selects the data transferred from the internal output databus of 128 bits via the data bus of 16 bits to generate final 16-bitdata D [15:0].

Memory cell row selection circuit 602 is also used in the data write-inand performs the row selection operation in accordance with internaladdress AO [22:0] in data writing.

Page mode instruction signal PAGE is supplied to read-out columnselection control circuit 606. In a normal operation mode, memory celldata of 16 bits is read out in a random sequence in accordance with anaddress signal in data read-out circuit 604. On the other hand, In thepage mode, data of eight words (128 bits) at the successive 4 addressesis read out from this data read-out circuit 604 and ⅛ selection issequentially performed in data transfer output circuit 608 to generate16-bit data. In memory cell array 10, data is stored in the MLCconfiguration.

FIG. 59 is a diagram schematically showing the configurations of dataread-out circuit 604 and data transfer output circuit 608 shown in FIG.58. In FIG. 59, data read-out circuit 604 includes: column selectiongates circuits (YG) 620 u and 620 l provided corresponding to blocks BAL[0] and BAL [1], respectively; a decoder 622 u that generates ¼ columnselection signals CLA and CLB to column selection gate circuit 620 u inaccordance with internal address bits AE [4:3] and block columnselection signal BALY [1]; and a decoder 622 l that generates ¼ columnselection signals CLA and CLB to column selection gate circuit 620 l inaccordance with internal address bits AE [4:3] and block columnselection signal BALY [0].

Main bit lines MLB [1023:512] are provided to column selection gatecircuit 620 u and main bit lines MBL [511:0] are provided to columnselection gate circuit 620 l. Column selection signals BLY [1] and BLY[0] are signals of the same logic and decoders 622 u and 622 l eachcarry out ⅛ selection to select 64 main bit lines from 512 main bitlines MBL. Column selection gate circuit 620 u couples the selected mainbit lines to internal read-out data lines BDE [127:64] while columnselection gate circuit 620 l couples the selected 64 main bit lines tointernal read-out data lines BDE [63:0].

Sense amplifier circuits (SA) 625 to 628 each 32-bit wide are providedto this internal read-out data lines BDE [127:0] of 128 bits. Senseamplifier circuit 625 is activated to perform the sensing of the data oninternal read-out data line BDE [31:0] in accordance with selectionsignal SE [3:0] to transmit the read-out data to internal output datalines ODE [31:0]. Sense amplifier circuit 626 carries out the sensingoperation of the data on internal read-out data lines BDE [63:32] whenactivated in accordance with sense selection signal SE [3:0], totransmit the read-out data of 32 bits to internal output data lines ODE[63:32]. Sense amplifier circuit 627 is activated in accordance withsense activation signal SE [7:4] to sense the data on internal read-outdata lines BDE [95:64] for transmitting the read-out data to internaloutput data lines ODE [95:64]. Sense amplifier circuit 628 is activatedin accordance with sense selection signal SE [7:4], to perform thesensing of the data on internal read-out data lines BDE [127:96] forgenerating and transmitting the read-out data to internal output datalines ODE [127:96].

Each of sense amplifier circuits 625 to 628 has 32 sense amplifiers eachbeing the same as that shown in FIG. 46.

Data transfer output circuit 608 includes: an upper transfer/outputcircuit 608U for outputting upper byte data DD [8:15]; and a lowertransfer/output circuit 608 L for generating lower 8-bit data DD [7:0].

Upper transfer/output circuit 608 u includes: a buffer circuit 631 thatis activated when transfer control signal ODELCS is activated, totransfer the data on internal output data lines ODE [63:0]; a buffercircuit 633 that transfers the 64 bit data on internal output data linesODE [127:64] upon activation of transfer control signal ODELC2S; a latchcircuit 635 u for latching the output data of buffer circuits 631 and633; a data selection circuit 636 u for selecting 8-bit data from the64-bit data of the latch circuit in accordance with selection signal SEL[7:0]; a swap circuit 637 u for selecting either spare data RDESP orinternal data IDE [8:15] from data selection circuit 636U in accordancewith spare hit instruction signal HIT; and an output buffer 638 u forgenerating output data DD [8:15] in accordance with transfer outputcontrol signal LOECUT.

Redundancy cells are arranged for replacing with a defective cell torepair the defective cell in the memory cell array. Spare hit signal HITis activated when a defective cell is selected and the selected memorycell data is replaced with data RDESP from a redundancy cell. Thearrangement of such redundancy cells are not shown.

Lower transfer/output circuit 608L includes: a buffer circuit 630 whichis activated upon activation of transfer control signal ODELCF, totransfer the data of internal output data lines ODE [63:0]; a buffercircuit 632 which is activated upon activation of transfer controlsignal ODELC2F, to transfer the 63 bit data of internal output datalines ODE [127:64]; a latch circuit 635 l of 64 bits that latches thetransfer data of buffer circuits 630 and 632; a data selection circuit636 l for selecting 8-bit data from the 64-bit data-of latch circuit 635l in accordance with data selection signal SEL [7:0]; a swap circuit 637l that selects either output data ID [7:0] of data selection circuit 636l or spare data RDESP in accordance with spare hit signal HIT; and anoutput buffer circuit 638 l that buffers the 8-bit output data of swapcircuit 637 l in accordance with output control signal LOECUT, togenerate data DD [7:0].

Block BAL [1] corresponds to the region where internal address bit AE[2] (AA [23]) is “1”, and block BAL [0] corresponds to the region wherethe internal address bit AE [2] is “0”. Data of external two words isstored in 16-bit memory cells of the same address in each of blocks BAL[0] and BAL [1]. In the data storage, upper word and lower word arestored in the upper byte region and the lower byte region, respectively.

Read-out address generation circuit 600 shown in FIG. 58 convertsaddress bit AA [23] externally applied to internal read-out columnaddress bit AE [2] and allocates address bit AA [2] externally appliedto internal read-out column address bit AE [23]. This internal read-outcolumn address bit AE [2] is used to perform selection between block BAL[1] and BAL [0]. Lower byte data and upper byte data of the 16-bit wordin the selected block are sensed by 2 sets of sense amplifier circuitsprovided to the selected block.

FIG. 60 is a timing chart representing the operations of read-outcircuit 604 and data transfer output circuit 608 shown in FIG. 59. Inthe following, the operations of these circuits shown in FIG. 59 aredescribed with reference to FIG. 60.

Data read-out/output circuit shown in FIG. 59 has a random access modefor selecting 16-bit data in a random sequence and a page mode forreading out 8 words in successive addresses in a sequential manner. Thenumber of sense amplifiers, which are simultaneously activated, isdifferent between the page mode operation and the random access mode,and the data read-out and transfer sequence is the same for the pagemode operation and for the random access mode operation. In either case,multi-level data stored by a memory cell is read out in accordance withthe serial sense scheme. In the following, the data read-out operationin the page mode is described.

As shown in FIG. 60, when data read-out access instruction ICE from thecommand user interface turns L level in accordance with the dataread-out command externally supplied, the operation of selecting memorycells is started in accordance with external address AA [23:0] currentlyapplied. First, precharging of the internal nodes to the power supplyvoltage level is performed in sense amplifier circuits 625 to 628 inaccordance with sense amplifier precharging instruction signal ATDEE. Inthis precharging operation, the column selection operation is performedby decoders 622 l and 622 u while column selection gate circuits 620 land 620 u each carry out the ⅛ selection operation to select 64 main bitlines MBL and connect the selected 64 main bit lines to internalread-out data lines BDD [127:0]. The precharging operation is performedon the selected main bit lines by the activated sense amplifiers, sothat the percharging current is supplied to the main bit lines selectedby column selection gate circuit 620 l and each main bit line is set ata predetermined read-out voltage level.

When the precharging operation is completed, one of sense activationsignals SE [3:0] and SE [7:4] is activated in accordance with internaladdress bit AE [2] (=AA [23]) in sense amplifier circuits 625 to 628.Here, as shown in FIG. 59, the state is assumed in which internaladdress bit AE [2] is “0” and sense amplifier activation signal SE [3:0]is activated.

When the precharging operation is completed, a sense amplifier isactivated to supply a reference current to the selected memory cell viathe selected main bit line, and the reference current and the cellcurrent are compared and the data read-out is effected. Data transfercontrol signal ODELCF is activated in accordance with the deactivationof the precharging instruction signal ATDEE, and buffer circuit 630transfers the 64-bit sense data from sense amplifier circuits 625 and626 to latch circuit 635 l.

Subsequently, the column selection operation is performed in accordancewith column selection activation signal CYDEN and one of data selectionsignals SEL [7:0] is driven to the selected state so that 8-bit data RDE[7:0] is outputted from data selection circuit 636 l to generateinternal output data IOD [7:0] via swap circuit 637 l. In FIG. 60,internal output data bit IOD [4] is representatively shown.

When the first sensing operation is completed, output data transfercontrol signal ODELCF enters the non-active state and buffer circuit 630is deactivated so that latch circuit 635 l enters the state of latchingthe supplied data. In addition, column selection activation signal CYDENis also deactivated so that data selection signals SEL [7:0] are alldeactivated. According to this first sensing operation, lower byte dataof successive two words stored in 16-bit memory cells is read out andthus each byte data of eight words at successive addresses is read out.

Precharging activation signal ATDEE is again activated and the secondprecharging operation is performed on the selected main bit lines andthe sense amplifiers. In this precharging operation, output transfercontrol signal ODELCS is activated and buffer circuit 631 is activatedso that the output data of sense amplifier circuits 625 and 626 istransferred to latch circuit 636 u. During the period of thisprecharging operation, data selection circuit 636 u carries out thecolumn selection operation in accordance with the active state of columnselection activation signal CYDEN and therefore, internal data bits IOD[8:15] from swap circuit 637 u are set to the state corresponding to thedata read out in the first sensing operation. In FIG. 60, the change ofdata bit IOD [11] is representatively shown.

When column selection activation signal CYDEN is deactivated, data bitIOD [11] attains the unselected state. Data bit IOD [4] also falls tothe L level because the output signal of data selection circuit 636 l isdeactivated. In FIG. 60, the output data bit of this lower data block608L is shown, and the data sensed at the time of the first sensing isshown being outputted from swap circuit 637 l continuously. According tothe second sensing operation, the upper byte data of the sequentialtwo-word data stored in 16-bit memory cells is read out and accordinglythe upper byte data of 8 words in total is read out.

When the second precharging operation is completed in accordance withthe deactivation of precharging activation instruction signal ATDEE andthe sensing operations of sense amplifier circuits 625 and 626 are againactivated, the output data of these sense amplifier circuits 625 and 626is transferred to latch circuit 635 u via buffer circuit 631 and arelatched therein.

When column selection activation signal CYDEN is again activated, one ofdata selection signals SEL [7:0] is driven to the selected state and theoutput signal of data selection circuit 636 u is driven to the statecorresponding to the data read out according to the second sensingoperation.

Subsequently, when data output control signal LOECUT is activated,output buffer circuits 638 l and 638 u are activated so that 8-bit dataIOD [7:0] and 8-bit data IOD [8:15] are outputted as data DD [7:0] andDD [8:15]. By utilizing this output control signal LOECUT, upper bytedata and lower byte data set in the definite state can be generated atthe same timing by output buffer circuits 630 u and 630 l precisely.

Here, data bit DD [8:15] is shown indicating that the data bit positionsare changed when the data is stored in the memory cell array and thedata of IO0 is compressed with the data of IO15 to be stored in the samememory cell.

In the case where data is read out from block BAL [1], sense amplifiercircuits 628 and 627 are activated and buffer circuits 633 and 632 areactivated in the first sensing operation and in the second sensingoperation, in accordance with output transfer control signals ODELC2Fand ODELC2S, and in the same manner, 64-bit data is stored in latchcircuits 635 l and 635 u.

Here, precharging instruction signal ATDEE is a signal corresponding tosense amplifier activation signal TXLATD shown in FIG. 46 and isactivated at a predetermined timing in accordance with the instructionfrom the command user interface in the external read-out mode of data.

In the case where data read-out is performed in a random sequence, oneof sense amplifier activation signals SE [7:0] is activated inaccordance with address bit AE [4:2]. In the case where internal addressbit AE [2] is “0”, for example, eight sense amplifiers are activated ineach of sense amplifier circuits 625 and 626 so that the sensingoperation of 16-bit data is performed. At this time, the data transferis performed in accordance with the serial sense scheme and thereforeoutput transfer control signals ODELCF and ODELCS are activated in thefirst sensing operation and in the second sensing operation,respectively, in accordance with internal read-out address bit AE [2].Subsequently, 8-bit data is selected from the 16-bit data transferredfrom the selected sense amplifiers in each of data selection circuits636 l and 636 u in accordance with selection signals SEL [7:0] togenerate external output data DD [8:15] and external output data DD[7:0]. In the page mode, addresses may sequentially be suppliedexternally and address bits AE [1:0] and AE [23] may be internallychanged sequentially to drive selection signals SEL [7:0] to theselected state sequentially. Data latched by the latch circuit issequentially read out, and therefore it is not necessary to carry outrow and column selections in the memory array, and thus data can be readout at high speed. In the case where addresses are changed internally,address signal bits may be updated in accordance with the clock signaland selection signals SEL [7:0] may be sequentially driven to theselected state.

Main bit line MBL and the internal read-out data line are divided intogroups in accordance with external data terminals (10) to carry out theselection operation in each group. Thus, data can be read out preciselyin the page mode and in the random access mode.

FIG. 61 is a diagram showing an example of the configuration of the partthat generates sense amplifier activation signals SE [7:0] shown in FIG.59. In FIG. 61, the sense amplifier activation signal generation partincludes: a decoding circuit 650 for decoding internal read-out columnaddress bits AE [4:3]; OR gate circuits 651 and 652 that receive outputsignal SF [3:0] of decoding circuit 650 and page mode instruction signalPAGE; an inverter 653 that receives internal read-out column address bitAE [2]; an AND gate circuit 654 that receives the output signal of ORgate circuit 651, internal read-out column address bit AE [2] and senseamplifier activation signal ATDSA; and an AND gate circuit 655 thatreceives the output signal of inverter 653, sense amplifier activationsignal ATDSA and the output signal of OR gate circuit 652.

Sense amplifier selection activation signal SE [7:4] is outputted fromAND gate circuit 654 and sense amplifier selection activation signal SE[3:0] is outputted from AND gate circuit 655.

Sense amplifier activation signal ATDSA is activated in the dataread-out at the same timing as sense amplifier activation signal MLC_ATDthat is generated in the verification.

In a normal operation mode, page mode instruction signal PAGE is at theL level and OR gate circuits 651 and 652 operate as buffer circuits. Inthis case, decoding circuit 650 decodes internal read-out address AE[4:3] of 2 bits to drive one of 4-bit selection signal SF [3:0] to theselected state. In the case where internal read-out column address bitAE [2] is at the L level, AND gate circuit 655 generates sense amplifierselection activation signal SE [3:0] on the basis of the selectionsignal SF [3:0] from OR gate circuit 652. At this time, sense amplifierselection activation signals SE [7:4] are all at the L level. In thecase where internal read-out column address bit AE [2] is at the Hlevel, the output signal of inverter 653 is at the L level and senseamplifier selection activation signal SE [7:4] is generated on the basisof selection signal SF [3:0] from OR gate circuit 651. At this time,sense amplifier selection activation signals SE [3:0] are all at the Llevel of the non-selected state.

When a page mode is designated, page mode instruction signal PAGEattains the H level and the output signals of OR gates 651 and 652 bothattains the H level. At this time, when internal read-out column addressbit AE [2] is at the H level, sense amplifier selection activationsignal SE [7:4] is driven to the selected state in accordance with senseamplifier activating signal ATDSA while sense amplifier selectionactivation signal SE [3:0] is maintained in the inactive state. Wheninternal read-out column address bit AE [2] is at the L level, senseamplifier selection activation signals SE [3:0] are all at the H levelwhile sense amplifier selection activation signals SE [7:4] are all atthe L level of the inactive state.

FIG. 62 is a diagram showing an example of the configurations of dataselection circuits 636 u and 636 l as well as the part that generatesselection signal SEL [7:0] shown in FIG. 59. The above data selectioncircuits 636 l and 636 u have the same configuration, and therefore FIG.62 representatively shows a data selection circuit 636. In addition,FIG. 62 shows the configuration of the part that corresponds to outputdata RDE [i] of one bit. Data selection circuit 636 is activated inaccordance with selection signals SEL [7:0], respectively, and selects 1bit of data bit OD [7:0] of 8 words at the time when activated, andincludes selection gate circuits G7 to G0 for generating data bit RDE[i].

Word data bits OD [7] to OD [0] supplied from the latch circuit in theprevious stage shown in FIG. 59 show the bits of the same position in 8words. Selection gate circuits G7 to G0 may be formed of a tri-statebuffer circuit or may be formed of a transmission gate circuit. One wordout of 8 words is designated by selection signal SEL [7:0] so that thecorresponding 1 bit is selected from data bits OD [7:0] so as togenerate internal read-out data RDE [i]. The basic configuration of thedata selection circuit shown in this FIG. 62 is provided to each ofoutput data bits RDE [7:0] and RDE [8:15].

Selection signal SEL [7:0] is generated by a decoding circuit 660activated when column selection activation signal CYDEN is activated, todecode internal read-out column address bits AE [23] and AE [1:0].Internal read-out column address bit AE [23] corresponds to externaladdress bit AA [2] and designates the upper word or the lower word. Onebit of 8-bit selection signal SEL [7:0] is driven to the selected stateby decoding internal read-out column address bits AE [23] and AE [1:0]of 3 bits.

In the configuration shown in this FIG. 59, upper word (16-bit externaldata) and lower word (16-bit external data) of 32-bit word are stored ineach of blocks BAL [1] and BAL [0], and thereby the lower word and theupper word of 8 words can be successively read out in the page mode.

FIG. 63 is a diagram schematically showing the configuration of the partthat generates a signal for carrying out operation controls of buffercircuits 630 to 633 shown in FIG. 59. In FIG. 63, the transfer controlsignal generation part includes: a gate circuit GG1 that receives basicfirst sense transfer control signal ODELF and internal read-out columnaddress bit AE [2] to generate data transfer control signal ODELCF; anAND gate circuit GG2 that receives internal read-out column address bitAE [2] and basic first sense transfer control signal ODELF to generatetransfer control signal ODELC2F; a gate circuit GG3 that receives basicsecond sense transfer control signal ODELS and internal read-out columnaddress bit AE [2] to generate second sense transfer control signalODELCS; and an AND gate circuit GG4 that receives basic second sensetransfer control signal ODELS and internal read-out column address bitAE [2] to generate second sense transfer control signal ODELC2S.

Gate circuits GG1 and GG2 operate as buffer circuits when internalread-out column address bit AE [2] is “0” and gate circuits GG2 and GG4operate as buffer circuits when internal read-out column address bit AE[2] is “1”. In the buffer circuit operation, these gate circuits GG1 andGG2 generate first sense transfer control signals ODELCF and ODELC2F inaccordance with basic first sense transfer control signal ODELF, andgate circuits GG3 and GG4 generate second sense transfer control signalsODELCS and ODELC2S in accordance with second sense transfer controlsignal ODELS. As a result, data can be transferred from the senseamplifier circuits arranged for the selection block of memory arrayblocks BAL [1] and BAL [0].

Here, first sense transfer control signals ODELF and ODELS in thecircuit shown in this FIG. 63, as well as sense amplifier prechargingactivation signal ATDEE and column selection activation signal CYDENshown in FIG. 60 are generated from the CPU shown in FIG. 4 inaccordance with the activation of read-out mode activation signal ICE.However, these transfer control signals may be generated on the basis ofthe internal clock signals by means of the hardware circuit as in theverification operation. The configuration of the sense activationcircuit in the verification operation can be utilized as an activationcircuit in the data read-out.

In addition, in the case where sense amplifier circuits 625 to 628 shownin FIG. 59 are utilized as sense amplifiers for verification, dataread-out in the random mode is performed in units of 16 bits, to becompared with the data read out from the page buffer: However, senseamplifiers 625 to 628 shown in FIG. 59 may be provided separately fromthe verification sense amplifiers and may be the sense amplifiers foroutputting the final data provided in common to all the banks in thecase of the multi-bank configuration inside the memory device.

In addition, as for the write driver for data write-in, write drivecircuits are provided respectively to internal read-out data lines BDE,and data write-in is performed in 16-bit units by selectively activatingthe write drivers in accordance with an address signal. The write drivecircuit is selectively activated at the time of the data write-inthrough the utilizing of the configuration similar to the configurationfor generating sense amplifier selection activation signal SE [7:0].

In addition, the number of address bits is not limited to 24 bits. It ismerely required that the first address bit that designates the arrayblock in the SLC configuration is exchanged with the most significantaddress bit in the MLC configuration, and this first address bit isutilized for identification of the upper word or lower word in the worddata stored in 16-bit memory cells in the MLC configuration.

In addition, the memory cell configuration is not limited to that of theNOR-type memory, but the present invention can be applied to any othertype of memory such as AND-type memory and NAND-type memory.

The present invention can be applied to a nonvolatile semiconductormemory device for storing multi-level data in a nonvolatile manner. Inparticular, the nonvolatile semiconductor memory device according to thepresent invention can be utilized in the application requiring storageof data in a nonvolatile manner in a small area.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1.-13. (canceled)
 14. A semiconductor memory device comprising: aplurality of memory cells aligned in rows and columns; a plurality ofreference cells; an averaging circuit for averaging currents flowingthrough said plurality of reference cells; and a current/voltageconversion circuit for converting a current generated by said averagingcircuit to a voltage to generate a reference voltage.
 15. Thesemiconductor memory device according to claim 14, further comprising: asense amplifier for generating a comparison current in accordance withsaid reference voltage and comparing the comparison current with acurrent flowing through a selected memory cell in said plurality ofmemory cells to detect data of the selected memory cell.
 16. Thesemiconductor memory device according to claim 14, wherein saidplurality of reference cells is aligned in rows and columns, and saidsemiconductor memory device further comprises a selection circuit forselecting reference cells in said plurality of reference cells inaccordance with an operation mode and coupling selected reference cellsto said averaging circuit.
 17. The semiconductor memory device accordingto claim 14, wherein said reference cells are the same in structure asthe memory cells and each reference cell has a transistor structurehaving a control gate and a floating gate connected together.
 18. Thesemiconductor memory device according to claim 14, wherein the referencecells comprise an insulating gate type field effect transistor having asize set in accordance with a level of the reference voltage to begenerated.
 19. A semiconductor memory device, comprising: a plurality ofmemory cells aligned in rows and columns; a plurality of word linesarranged corresponding to the memory cell rows, and connecting to thememory cells in corresponding rows; a circuit for generating a firstvoltage at a predetermined voltage level to be transmitted onto aselected word line in said plurality of word lines; a division circuitfor generating a divided voltage by dividing said first voltage; areference cell selectively rendered conductive in accordance with adivided voltage; a reference voltage generation circuit for generating areference voltage in accordance with a current flowing said referencecell; and a sense amplifier circuit for generating a comparisonreference current in accordance with the reference voltage generated bysaid reference voltage generation circuit and comparing the comparisoncurrent with a current flowing through a selected memory cell to detectmemory cell data in accordance with a result of comparison.
 20. Thesemiconductor memory device according to claim 19, wherein saidreference cell is the same in structure as the memory cells and has atransistor structure having a control gate and a floating gateinterconnected.
 21. The semiconductor memory device according to claim19, wherein said reference cell includes an insulating gate type fieldeffect transistor having a size set in accordance with a level of thereference voltage to be generated. 22-25. (canceled)